EZ-USB Datasheet, PDF (266/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

Addr
7FA8
7FA9
7FAA
7FAB
7FAC
7FAD
7FAE
7FAF
7FB0
7FB1
7FB2
7FB3
7FB4
7FB5
7FB6
7FB7
7FB8
7FB9
7FBA
7FBB
7FBC
7FBD
7FBE
7FBF
7FC0
7FC1
7FC2
7FC3
7FC4
7FC5
7FC6
7FC7
7FC8
7FC9
7FCA
7FCB
7FCC
7FCD
7FCE
7FCF
7FD0
7FD1
7FD2
7FD3
Name
Interrupts
IVEC
IN07IRQ
OUT07IRQ
USBIRQ
IN07IEN
OUT07IEN
USBIEN
USBBAV
IBNIRQ
IBNIE
BPADDRH
BPADDRL
Bulk Endpoints 0-7
EP0CS
IN0BC
IN1CS
IN1BC
IN2CS
IN2BC
IN3CS
IN3BC
IN4CS
IN4BC
IN5CS
IN5BC
IN6CS
IN6BC
IN7CS
IN7BC
OUT0BC
OUT1CS
OUT1BC
OUT2CS
OUT2BC
OUT3CS
OUT3BC
OUT4CS
OU4TBC
OUT5CS
OUT5BC
OUT6CS
OUT6BC
OUT7CS
OUT7BC
EZ-USB TRM v 1.9
EZ-USB Registers
Description
D7
D6
D5
D4
D3
D2
D1
D0
Interrupt Vector
EPIN Interrupt Request
EPOUT Interrupt Request
USB Interrupt Request
EP0-7IN Int Enables
EP0-7OUT Int Enables
USB Int Enables
Breakpoint & Autovector
IBN Interrupt request
IBN Interrupt Enable
Breakpoint Address H
Breakpoint Address L
0
IN7IR
OUT7IR
*
IN7IEN
OUT7IEN
*
*
A15
A7
IV4
IN6IR
OUT6IR
*
IN6IEN
OUT6IEN
*
*
EP6IN
EP6IN
A14
A6
IV3
IN5IR
OUT5IR
IBNIR
IN5IEN
OUT5IEN
IBNIE
*
EP5IN
EP5IN
A13
A5
IV2
IN4IR
OUT4IR
URESIR
IN4IEN
OUT4IEN
URESIE
*
EP4IN
EP4IN
A12
A4
IV1
IN3IR
OUT3IR
SUSPIR
IN3IEN
OUT3IEN
SUSPIE
BREAK
EP3IN
EP3IN
A11
A3
IV0
IN2IR
OUT2IR
SUTOKIR
IN2IEN
OUT2IEN
SUTOKIE
BPPULSE
EP2IN
EP2IN
A10
A2
0
IN1IR
OUT1IR
SOFIR
IN1IEN
OUT1IEN
SOFIE
BPEN
EP1IN
EP1IN
A9
A1
0
IN0IR
OUT0IR
SUDAVIR
IN0IEN
OUT0IEN
SUDAVIE
AVEN
EP0IN
EP0IN
A8
A0
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
(reserved)
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
Control & Status
Byte Count
*
*
*
*
OUTBSY
INBSY
HSNAK EP0STALL
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
in1bsy
in1stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
in2bsy
in2stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
in3bsy
in3stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
in4bsy
in4stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
in5bsy
in5stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
in6bsy
in6stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
in7bsy
in7stl
*
d6
d5
d4
d3
d2
d1
d0
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
out1bsy
out1stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
out2bsy
out2stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
out3bsy
out3stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
out4bsy
out4stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
out5bsy
out5stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
out6bsy
out6stl
*
d6
d5
d4
d3
d2
d1
d0
*
*
*
*
*
*
out7bsy
out7stl
*
d6
d5
d4
d3
d2
d1
d0
EZ-USB Registers
Notes
1=request
1=request
1=request
1=enabled
1=enabled
1=enabled
1=enabled
1=request
1=enabled
For EP0IN and EP0OUT
* this bits are random
at power-on. Once
operational, these bits
read as zeros.
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