EZ-USB Datasheet, PDF (222/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

12.12 Endpoint 0 Control and Status Registers
EP0CS
b7
b6
-
-
R
R
0
0
Endpoint Zero Control and Status
b5
b4
b3
b2
-
-
OUTBSY INBSY
R
R
R
R
0
0
1
0
7FB4
b1
HSNAK
R/W
0
b0
EP0STALL
R/W
0
IN0BC
Endpoint Zero IN Byte Count
7FB5
b7
b6
b5
b4
b3
b2
b1
b0
-
BC6
BC5
BC4
BC3
BC2
BC1
BC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
OUT0BC
Endpoint Zero OUT Byte Count
7FC5
b7
b6
b5
b4
b3
b2
b1
b0
-
BC6
BC5
BC4
BC3
BC2
BC1
BC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Figure 12-25. Port Configuration Registers
These registers control EZ-USB CONTROL endpoint zero. Because endpoint zero is a bi-
directional endpoint, the IN and OUT functionality is controlled by a single control and
status (CS) register, unlike endpoints 1-7, which have separate INCS and OUTCS regis-
ters.
Bit 3:
OUTBSY OUT Endpoint Busy
OUTBSY is a read-only bit that is automatically cleared when a SETUP token arrives.
The 8051 sets the OUTBSY bit by writing a byte count to EPOUTBC.
EZ-USB TRM v1.9
Chapter 12. EZ-USB Registers
Page 12-29