EZ-USB Datasheet, PDF (50/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

2.8 Power Control
The EZ-USB core implements a power-down mode that allows it to be used in USB bus
powered devices that must draw no more than 500 µA when suspended. Power control is
accomplished using a combination of 8051 and EZ-USB core resources. The mechanism
by which EZ-USB powers down for suspend, and then re-powers to resume operation, is
described in detail in Chapter 11, “EZ-USB Power Management.”
A suspend operation uses three 8051 resources, the idle mode and two interrupts. Many
enhanced 8051 architectures provide power control similar (or identical) to the EZ-USB
enhanced 8051 core.
A USB suspend operation is indicated by a lack of bus activity for 3 ms. The EZ-USB
core detects this, and asserts an interrupt request via the USB interrupt (8051 INT2). The
ISR (Interrupt Service Routine) turns off external sub-systems that draw power. When
ready to suspend operation, the 8051 sets an SFR bit, PCON.0. This bit causes the 8051 to
suspend, waiting for an interrupt.
When the 8051 sets PCON.0, a control signal from the 8051 to the EZ-USB core causes
the core to shut down the 12-MHz oscillator and internal PLL. This stops all internal
clocks to allow the EZ-USB core and 8051 to enter a very low power mode.
The suspended EZ-USB chip can be awakened two ways: USB bus activity may resume,
or an EZ-USB pin (WAKEUP#) can be asserted to activate a USB Remote Wakeup. Either
event triggers the following chain of events:
• The EZ-USB core re-starts the 12-MHz oscillator and PLL, and waits for the
clocks to stabilize
• The EZ-USB core asserts a special, high-priority 8051 interrupt to signal a
‘resume’ interrupt.
• The 8051 vectors to the resume ISR, and upon completion resumes executing code
at the instruction following the instruction that set the PCON.0 bit to 1.
EZ-USB TRM v1.9
Chapter 2. EZ-USB CPU
Page 2-5