EZ-USB Datasheet, PDF (48/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

2.5 EZ-USB Internal RAM
FF _{Upper 128}
bytes
80 ^{Indirect Addr}
7F _{Lower 128}
bytes
00 ^{Direct Addr}
SFR Space
Direct Addr
Figure 2-1. 8051 Registers
Like the standard 8051, the EZ-USB 8051 core contains 128 bytes of register RAM at 00-
7F, and a partially populated SFR register space at 80-FF. An additional 128 indirectly
addressed registers (sometimes called “IDATA”) are also available at 80-FF.
All internal EZ-USB RAM, which includes program/data memory, bulk endpoint buffer
memory, and the EZ-USB register set, is addressed as add-on 8051 memory. The 8051
reads or writes these bytes as data using the MOVX (move external) instruction. Even
though the MOVX instruction implies external memory, the EZ-USB RAM and register
set is actually inside the EZ-USB chip. External memory attached to the AN2131Q
address and data busses can also be accessed by the MOVX instruction. The EZ-USB
core encodes its memory strobe and select signals (RD#, WR#, CS#, and OE#) to elimi-
nate the need for external logic to separate the internal and external memory spaces.
2.6 I/O Ports
A standard 8051 communicates with its IO ports 0-3 through four Special Function Regis-
ters (SFRs). Standard 8051 IO pins are quasi-bidirectional with weak pullups that briefly
drive high only when the pin makes a zero-to-one transition.
The EZ-USB core implements IO ports differently than a standard 8051, as described
in Chapter 4, "EZ-USB Input/Output." Instead of using the 8051 IO ports and SFRs, the
EZ-USB core implements a flexible IO system that is controlled via EZ-USB register set.
Each EZ-USB IO pin functions identically, having the following resources:
• An output latch. Used when the pin is an output port.
• A bit that indicates the state of the IO pin, regardless of its configuration (input or
output).
EZ-USB TRM v1.9
Chapter 2. EZ-USB CPU
Page 2-3