EZ-USB Datasheet, PDF (104/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

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Data Packet
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H/S Pkt
(OUTnBC loaded,
OUTnBSY=1)
EPnOUT Interrupt,
OUTnBSY=0
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Data Packet _{H/S Pkt}
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Load OUTnBC (any value),
causes OUTnBSY=1
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EPnOUT Interrupt,
OUTnBSY=0
Figure 6-4. Anatomy of a Bulk OUT Transfer
Each EZ-USB bulk OUT endpoint has a byte count register, which serves two purposes.
The 8051 reads the byte count register to determine how many bytes were received during
the last OUT transfer from the host. The 8051 writes the byte count register (with any
value) to tell the EZ-USB core that is has finished reading bytes from the buffer, making
the buffer available to accept the next OUT transfer. The OUT endpoints come up (after
reset) armed, so the byte count register writes are required only for OUT transfers after the
first one.
In the bulk OUT transfer illustrated in Figure 6-4, the 8051 has previously loaded the end-
point’s byte count register with any value to arm receipt of the next OUT transfer. Loading
the byte count register causes the EZ-USB core to set the OUT endpoint’s busy bit to 1,
indicating that the 8051 should not use the endpoint’s buffer.
The host issues an OUT token (1), followed by a packet of data (2), which the USB core
acknowledges, clears the endpoint’s busy bit and generates an interrupt request (3). This
notifies the 8051 that the endpoint buffer contains valid USB data. The 8051 reads the
endpoint’s byte count register to find out how many bytes were sent in the packet, and
transfers that many bytes out of the endpoint buffer.
In a multi-packet transfer, the host then issues another OUT token (4) along with the next
data packet (5). If the 8051 has not finished emptying the endpoint buffer, the EZ-USB FX
EZ-USB TRM v1.9
Chapter 6. EZ-USB CPU
Page 6-7