EZ-USB Datasheet, PDF (130/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

Each bulk endpoint (IN or OUT) has a STALL bit in its Control and Status register (bit 0).
If the CPU sets this bit, any requests to the endpoint return a STALL handshake rather
than ACK or NAK. The Get Status-Endpoint request returns the STALL state for the end-
point indicated in byte 4 of the request. Note that bit 7 of the endpoint number EP (byte 4)
specifies direction.
Endpoint zero is a CONTROL endpoint, which by USB definition is bi-directional.
Therefore, it has only one stall bit.
About STALL
The USB STALL handshake indicates that something unexpected has happened. For
instance, if the host requests an invalid alternate setting or attempts to send data to a non-
existent endpoint, the device responds with a STALL handshake over endpoint zero
instead of ACK or NAK.
Stalls are defined for all endpoint types except ISOCHRONOUS, which do not employ
handshakes. Every EZ-USB bulk endpoint has its own stall bit. The 8051 sets the stall
condition for an endpoint by setting the stall bit in the endpoint’s CS register. The host
tells the 8051 to set or clear the stall condition for an endpoint using the Set_Feature/Stall
and Clear_Feature/Stall requests.
An example of the 8051 setting a stall bit would be in a routine that handles endpoint
zero device requests. If an undefined or non-supported request is decoded, the 8051
should stall EP0. (EP0 has a single stall bit because it is a bi-directional endpoint.)
Once the 8051 stalls an endpoint, it should not remove the stall until the host issues a
Clear_Feature/Stall request. An exception to this rule is endpoint 0, which reports a stall
condition only for the current transaction, and then automatically clears the stall condi-
tion. This prevents endpoint 0, the default CONTROL endpoint, from locking out device
requests.
EZ-USB TRM v1.9
Chapter 7. EZ-USB CPU
Page 7-9