EZ-USB Datasheet, PDF (210/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

Bit 5:
LASTRD Last Data Read
To read data over the I²C bus, an I²C master floats the SDA line and issues clock pulses on
the SCL line. After every eight bits, the master drives SDA low for one clock to indicate
ACK. To signal the last byte of the read transfer, the master floats SDA at ACK time to
instruct the slave to stop sending. This is controlled by the 8051 by setting LastRD=1
before reading the last byte of a read transfer. The I²C controller clears the LastRD bit at
the end of the transfer (at ACK time).
Note
Setting LastRD does not automatically generate a STOP condition. The 8051 should
also set the STOP bit at the end of a read transfer.
Bit 4-3:
ID1,ID0 Boot EEPROM ID
These bits are set by the boot loader to indicate whether an 8-bit address or 16-bit address
EEPROM at slave address 000 or 001 was detected at power-on. Normally, they are used
for debug purposes only.
Bit 2:
BERR
Bus Error
This bit indicates an I²C bus error. BERR=1 indicates that there was bus contention,
which results when an outside device drives the bus LO when it shouldn’t, or when
another bus master wins arbitration, taking control of the bus. BERR is cleared when
8051 reads or writes the IDATA register.
Bit 1:
ACK
Acknowledge bit
Every ninth SCL or a write transfer the slave indicates reception of the byte by asserting
ACK. The EZ-USB controller floats SDA during this time, samples the SDA line, and
updates the ACK bit with the complement of the detected value. ACK=1 indicates
acknowledge, and ACK=0 indicates not-acknowledge. The EZ-USB core updates the
ACK bit at the same time it sets DONE=1. The ACK bit should be ignored for read trans-
fers on the bus.
EZ-USB TRM v1.9
Chapter 12. EZ-USB Registers
Page 12-17