EZ-USB Datasheet, PDF (331/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

Table C-19. Interrupt Flags, Enables, and Priority Control
Interrupt
Description
Flag
Enable
Priority
Control
RESUME
INT0
TF0
INT1
TF1
TI_0 or RI_0
TF2 or EXF2
TI_1 or RI_1
USB
I²C
INT4
INT5
INT6
Resume interrupt EICON.4
EICON.5
External interrupt 0 TCON.1
IE.0
Timer 0 interrupt TCON.5
IE.1
External interrupt 1 TCON.3
IE.2
Timer 1 interrupt TCON.7
IE.3
Serial port 0
SCON0.0 (RI.0),
IE.4
transmit or receive SCON0.1 (Ti_0)
Timer 2 interrupt T2CON.7 (TF2),
IE.5
T2CON.6 (EXF2)
Serial port 1
SCON1.0 (RI_1), IE.6
transmit or receive SCON1.1 (TI_1)
USB interrupt
EXIF.4
EIE.0
I²C interrupt
EXIT.5
EIE.1
External interrupt 4 EXIF.6
EIE.2
External interrupt 5 EXIF.7
EIE.3
External INT 6
EICON.3
EIE.4
N/A
IP.0
IP.1
IP.2
IP.3
IP.4
IP.5
IP.6
EIP.0
EIP.1
EIP.2
EIP.3
EIP.4
C.4.3 Interrupt Sampling
The internal timers and serial ports generate interrupts by setting their respective SFR
interrupt flag bits. External interrupts are sampled once per instruction cycle.
INT0 and INT1 are both active low and can be programmed to be either edge-sensitive or
level-sensitive, through the IT0 and IT1 bits in the TCON SFR. For example, when IT0 = 0,
INT0 is level-sensitive and the 8051 core sets the IE0 flag when the INT0# pin is sampled
low. When IT0 = 1, INT0 is edge-sensitive and the 8051 sets the IE0 flag when the INT0#
pin is sampled high then low on consecutive samples.
The remaining five interrupts (INT 4-6, USB & I²C Interrupts) are edge-sensitive only. INT6
and INT4 are active high and INT5 is active low.
To ensure that edge-sensitive interrupts are detected, the corresponding ports should be held
high for 4 CLK24 cycles and then low for 4 CLK24 cycles. Level-sensitive interrupts are not
EZ-USB TRM v1.9
Appendix C: 8051 Hardware Description
C - 35