EZ-USB Datasheet, PDF (226/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

Bit 0:
INnSTL IN Endpoint (1-7) Stall
The 8051 sets this bit to “1” to stall an endpoint, and to “0” to clear a stall.
When the stall bit is “1,” the EZ-USB core returns a STALL Handshake for all requests to
the endpoint. This notifies the host that something unexpected has happened.
The 8051 sets an endpoint’s stall bit under two circumstances:
1. The host sends a “Set_Feature—Endpoint Stall” request to the specific endpoint.
2. The 8051 encounters any show stopper error on the endpoint, and sets the stall bit
to tell the host to halt traffic to the endpoint.
The 8051 clears an endpoint’s stall bit under two circumstances:
1. The host sends a “Clear_Feature--Endpoint Stall” request to the specific endpoint.
2. The 8051 receives some other indication from the host that the stall should be
cleared (this is referred to as “host intervention” in the USB Specification). This
indication could be a USB bus reset.
All stall bits are automatically cleared when the EZ-USB chip ReNumerates™ by pulsing
the DISCON bit HI.
EZ-USB TRM v1.9
Chapter 12. EZ-USB Registers
Page 12-33