EZ-USB Datasheet, PDF (214/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

USBIRQ
USB Interrupt Request
7FAB
b7
b6
-
-
R/W
R/W
0
0
* AN2122/AN2126 only.
b5
IBNIR*
R/W
0
b4
URESIR
R/W
0
b3
SUSPIR
R/W
0
b2
SUTOKIR
R/W
0
b1
SOFIR
R/W
0
Figure 12-18. USB Interrupt Request (IRQ) Registers
b0
SUDAVIR
R/W
0
USBIRQ indicates the interrupt request status of the USB reset, suspend, setup token, start
of frame, and setup data available interrupts.
Bit 5:
IBNIR
IN Bulk NAK Interrupt Request
This bit is in the AN2122 and AN2126 versions only. The EZ-USB core sets this bit when
any of the IN bulk endpoints responds to an IN token with a NAK. This interrupt occurs
when the host sends an IN token to a bulk IN endpoint which has not been armed by the
8051 writing its byte count register. Individual enables and requests (per endpoint) are
controlled by the IBNIRQ and IBNIEN registers (7FB0, 7FB1).
Bit 4:
URESIR USB Reset Interrupt Request
The EZ-USB core sets this bit to “1” when it detects a USB bus reset.
Because this bit can change state while the 8051 is in reset, it may be active when the 8051
comes out of reset, although it is reset to “0” by a power-on reset. Write a “1” to this bit to
clear the interrupt request. See Chapter 10, "EZ-USB Resets" for more information about
this bit.
Bit 3:
SUSPIR USB Suspend Interrupt Request
The EZ-USB core sets this bit to “1” when it detects USB SUSPEND signaling (no bus
activity for 3 ms). Write a “1” to this bit to clear the interrupt request.
Because this bit can change state while the 8051 is in reset, it may be active when the 8051
comes out of reset, although it is reset to “0” by a power-on reset. See Chapter 11, "EZ-
USB Power Management" for more information about this bit.
EZ-USB TRM v1.9
Chapter 12. EZ-USB Registers
Page 12-21