EZ-USB Datasheet, PDF (148/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

The EZ-USB core uses the ISOSEND0 bit to determine what to do if:
• The 8051 does not load any bytes to an INnDATA register during the previous
frame, and
• An IN token for that endpoint arrives from the host.
If ISOSEND0=0 (the default value), the EZ-USB core does not respond to the IN token.
If ISOSEND0=1, the EZ-USB core sends a zero-length data packet in response to the IN
token. Which action to take depends on the overall system design. The ISOSEND0 bit
applies to all of the isochronous IN endpoints, EP8IN through EP15IN.
8.2.2 IN Data Transfers
When an SOF interrupt occurs, the 8051 is presented with empty IN FIFOs that it fills
with data to be transferred to the host during the next frame. The 8051 has 1 ms to transfer
data into these FIFOs before the next SOF interrupt arrives.
To respond to the SOF interrupt, the 8051 clears the USB interrupt (8051 INT2), and
clears the SOFIR (Start Of Frame Interrupt Request) bit writing a “1” to it. Then, the 8051
loads data into the appropriate isochronous endpoint. The EZ-USB core keeps track of the
number of bytes the 8051 loads to each INnDATA register, and subsequently transfers the
correct number of bytes in response to the USB IN token during the next frame.
The EZ-USB FIFO swap occurs every SOF, even if during the previous frame the host did
not issue an IN token to read the isochronous FIFO data, or if the host encountered an
error in the data. USB isochronous data has no re-try mechanism like bulk data.
8.3 Isochronous OUT Transfers
OUT transfers travel from host to device. Figure 8-3 shows the EZ-USB registers and bits
associated with isochronous OUT transfers.
EZ-USB TRM v1.9
Chapter 8. EZ-USB CPU
Page 8-3