EZ-USB Datasheet, PDF (180/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

10 EZ-USB Resets
10.1 Introduction
The EZ-USB chip has three resets:
• A Power-On Reset (POR), which turns on the EZ-USB chip in a known state.
• An 8051 reset, controlled by the EZ-USB core.
• A USB bus reset, sent by the host to reset a device.
This chapter describes the effects of these three resets.
10.2 EZ-USB Power-On Reset (POR)
Vcc
RESET
RES
8051
CPUCS.0
(1 at PWR ON)
RES
EZ-USB Core
USB Bus
Reset
24 MHz
12
MHz
XIN
XOUT
Oscillator
48 MHz
PLL
÷2
CLK24
Figure 10-1. EZ-USB Resets
When power is first applied to the EZ-USB chip, the external R-C circuit holds the EZ-
USB core in reset until the on-chip PLL stabilizes. The CLK24 pin is active as soon as
power is applied. The 8051 may clear an EZ-USB control bit, CLK24OE, to inhibit the
CLK24 output pin for EMI-sensitive applications that do not need this signal. External
logic can force a chip reset by pulling the RESET pin HI. The RESET pin is normally
EZ-USB TRM v1.9
Chapter 10. EZ-USB Resets
Page 10-1