EZ-USB Datasheet, PDF (176/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

9.12 I²C Interrupt
DONE
RD or WR
I2DAT register
EZ-USB 8051
S
R
I²C Interrupt
Request
S
R
EXIF.5(0)
EIE.1
EXIF.5(rd)
8051 I²C
Interrupt
(INT3)
I2CS ^START
STOP
LASTRD
ID1
I2DAT ^D7
D6
D5
D4
ID0
BERR
ACK
DONE
D3
D2
D1
D0
Figure 9-8. I²C Interrupt Enable Bits and Registers
Chapter 4, "EZ-USB Input/Output" describes the 8051 interface to the EZ-USB I²C con-
troller. The 8051 uses two registers, I2CS (I²C Control and Status) and I2DAT (I²C Data)
to transfer data over the I²C bus. The EZ-USB core signals completion of a byte transfer
by setting the DONE bit (I2CS.0) high, which also sets an I²C interrupt request latch
(Figure 9-8). This interrupt request is routed to the 8051 INT3 interrupt.
The 8051 enables the I²C interrupt by setting EIE.1=1. The 8051 determines the state of
the interrupt request flag by reading EXIF.5, and resets the INT3 interrupt request by writ-
ing a zero to EXIF.5. Any 8051 read or write to the I2DAT or I2CS register automatically
clears the I²C interrupt request.
9.13 In Bulk NAK Interrupt - (AN2122/AN2126 only)
The EZ-USB family responds to an IN token from the host by loading an IN endpoint
buffer and then arming the endpoint by loading a byte count for the endpoint. After the
host successfully receives the IN data, the 8051 receives an EP-IN interrupt, signifying
that the IN endpoint buffer is once again ready to accept data.
EZ-USB TRM v1.9
Chapter 9. EZ-USB Interrupts
Page 9-13