EP3SE110F1152I3N Datasheet, PDF (98/341 Pages) Altera Corporation – Stratix III Device Handbook

1–88
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–57. EP3SL70 Column Pins Output Timing Parameters (Part 3 of 4)
I/O Standard
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
4mA
GCLK
PLL
t_co
3.056
3.046
3.279
3.269
4.646 5.054 5.571 5.431 5.649 5.181 5.698 5.560 5.717 ns
4.636 5.043 5.561 5.421 5.639 5.170 5.688 5.550 5.707 ns
GCLK t_co
6mA
GCLK
PLL
t_co
DIFFERENTIAL
1.5-V SSTL
GCLK t_co
CLASS I
8mA
GCLK
PLL
t_co
3.046
3.039
3.038
3.060
3.269
3.263
3.261
3.283
4.639 5.047 5.565 5.425 5.643 5.175 5.693 5.555 5.712 ns
4.632 5.041 5.559 5.419 5.637 5.168 5.687 5.549 5.706 ns
4.629 5.038 5.556 5.416 5.634 5.165 5.683 5.545 5.702 ns
4.650 5.058 5.575 5.435 5.653 5.185 5.703 5.565 5.722 ns
GCLK t_co
10mA _GCLK
PLL
t_co
3.050
3.045
3.272
3.268
4.629 5.035 5.550 5.410 5.628 5.161 5.676 5.538 5.695 ns
4.629 5.035 5.551 5.411 5.629 5.162 5.678 5.540 5.697 ns
GCLK t_co
12mA _GCLK
PLL
t_co
3.043
3.035
3.266
3.257
4.628 5.034 5.549 5.409 5.627 5.161 5.677 5.539 5.696 ns
4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 ns
GCLK t_co
DIFFERENTIAL ^8mA
1.5-V SSTL
GCLK
PLL
t_co
CLASS II
GCLK t_co
16mA _GCLK
PLL
t_co
3.036
3.035
3.047
3.043
3.259
3.256
3.269
3.266
4.624 5.031 5.548 5.408 5.626 5.159 5.676 5.538 5.695 ns
4.607 5.012 5.526 5.386 5.604 5.138 5.652 5.514 5.671 ns
4.625 5.030 5.544 5.404 5.622 5.157 5.671 5.533 5.690 ns
4.626 5.032 5.548 5.408 5.626 5.159 5.675 5.537 5.694 ns
GCLK t_co
4mA
GCLK
PLL
t_co
3.033
3.031
3.255
3.253
4.615 5.021 5.536 5.396 5.614 5.148 5.663 5.525 5.682 ns
4.613 5.018 5.534 5.394 5.612 5.146 5.661 5.523 5.680 ns
GCLK t_co
6mA
GCLK
PLL
t_co
DIFFERENTIAL
1.8-V SSTL
GCLK t_co
CLASS I
8mA
GCLK
PLL
t_co
3.031
3.035
3.061
3.047
3.254
3.257
3.286
3.272
4.616 5.023 5.539 5.399 5.617 5.150 5.667 5.529 5.686 ns
4.613 5.018 5.533 5.393 5.611 5.145 5.660 5.522 5.679 ns
4.658 5.066 5.583 5.443 5.661 5.193 5.710 5.572 5.729 ns
4.646 5.055 5.573 5.433 5.651 5.183 5.701 5.563 5.720 ns
GCLK t_co
10mA _GCLK
PLL
t_co
3.035
3.035
3.259
3.259
4.629 5.037 5.555 5.415 5.633 5.165 5.683 5.545 5.702 ns
4.632 5.041 5.559 5.419 5.637 5.169 5.688 5.550 5.707 ns
GCLK t_co
12mA _GCLK
PLL
t_co
3.031
3.035
3.255
3.257
4.625 5.033 5.552 5.412 5.630 5.162 5.680 5.542 5.699 ns
4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 ns
GCLK t_co
DIFFERENTIAL ^8mA
1.8-V SSTL
GCLK
PLL
t_co
CLASS II
GCLK t_co
16mA _GCLK
PLL
t_co
3.036
3.064
3.053
3.048
3.259
3.289
3.277
3.273
4.626 5.034 5.551 5.411 5.629 5.161 5.679 5.541 5.698 ns
4.657 5.064 5.581 5.441 5.659 5.192 5.708 5.570 5.727 ns
4.645 5.052 5.569 5.429 5.647 5.180 5.696 5.558 5.715 ns
4.645 5.053 5.570 5.430 5.648 5.181 5.698 5.560 5.717 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation