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EP3SE110F1152I3N Datasheet, PDF (149/341 Pages) Altera Corporation – Stratix III Device Handbook
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–139
Table 1–77 lists the EP3SL150 column pins output timing parameters for differential
I/O standards.
Table 1–77. EP3SL150 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
Clock
Fast Model
Industrial Commercial
C2
VCCL=
1.1 V
C3
VCCL=
1.1 V
C4
VCCL=
1.1 V
C4L
VCCL= VCCL=
1.1 V 0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL= VCCL=
1.1 V 0.9 V
Units
LVDS_E_1R
GCLK tco
—
GCLK
PLL
tco
3.100
1.308
3.330
1.480
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 ns
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 ns
LVDS_E_3R
GCLK tco
—
GCLK
PLL
tco
3.096
1.304
3.333
1.483
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 ns
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 ns
MINI-
LVDS_E_1R
GCLK tco
—
GCLK
PLL
tco
3.100
1.308
3.330
1.480
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 ns
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 ns
MINI-
LVDS_E_3R
GCLK tco
—
GCLK
PLL
tco
3.096
1.304
3.333
1.483
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 ns
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 ns
RSDS_E_1R
GCLK tco
—
GCLK
PLL
tco
3.100
1.308
3.330
1.480
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 ns
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 ns
RSDS_E_3R
GCLK tco
—
GCLK
PLL
tco
3.096
1.304
3.333
1.483
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 ns
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 ns
GCLK tco
4mA
GCLK
PLL
tco
3.127
1.335
3.363
1.513
4.758 5.157 5.670 5.531 5.815 5.280 5.792 5.656 5.889 ns
1.956 2.056 2.272 2.283 2.310 2.161 2.379 2.389 2.297 ns
GCLK tco
6mA
GCLK
PLL
tco
DIFFERENTIAL
1.2-V HSTL
GCLK tco
CLASS I
8mA
GCLK
PLL
tco
3.117
1.325
3.117
1.325
3.353
1.503
3.353
1.503
4.748 5.146 5.660 5.521 5.805 5.269 5.782 5.646 5.879 ns
1.946 2.045 2.262 2.273 2.300 2.150 2.369 2.379 2.287 ns
4.751 5.150 5.664 5.525 5.809 5.274 5.787 5.651 5.884 ns
1.949 2.049 2.266 2.277 2.304 2.155 2.374 2.384 2.292 ns
GCLK tco
10mA GCLK
PLL
tco
3.110
1.318
3.347
1.497
4.744 5.144 5.658 5.519 5.803 5.267 5.781 5.645 5.878 ns
1.942 2.043 2.260 2.271 2.298 2.148 2.368 2.378 2.286 ns
GCLK tco
12mA GCLK
PLL
tco
3.109
1.317
3.345
1.495
4.741 5.141 5.655 5.516 5.800 5.264 5.777 5.641 5.874 ns
1.939 2.040 2.257 2.268 2.295 2.145 2.364 2.374 2.282 ns
DIFFERENTIAL
GCLK tco
1.2-V HSTL
CLASS II
16mA GCLK
PLL
tco
3.131
1.339
3.367
1.517
4.762 5.161 5.674 5.535 5.819 5.284 5.797 5.661 5.894 ns
1.960 2.060 2.276 2.287 2.314 2.165 2.384 2.394 2.302 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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