EP3SE110F1152I3N Datasheet, PDF (165/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–155
Table 1–83. EP3SL200 Column Pins Output Timing Parameters (Part 4 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
2mA
GCLK t_co
GCLK
PLL ^tco
3.730
4.129
3.730
4.129
5.556 5.815 6.395 6.252 6.657 5.815 6.395 6.252 6.657 ns
6.191 6.455 7.099 6.927 7.414 6.455 7.099 6.927 7.414 ns
GCLK t_co 3.607
3.607 5.330 5.553 6.109 5.966 6.371 5.553 6.109 5.966 6.371 ns
4mA _GCLK
PLL ^tco
4.006
4.006 5.965 6.193 6.813 6.641 7.128 6.193 6.813 6.641 7.128 ns
1.2 V
GCLK t_co 3.569
3.569 5.238 5.464 5.996 5.853 6.258 5.464 5.996 5.853 6.258 ns
6mA _GCLK
PLL ^tco
3.968
3.968 5.873 6.104 6.700 6.528 7.015 6.104 6.700 6.528 7.015 ns
8mA
GCLK t_co
GCLK
PLL ^tco
3.522
3.921
3.522
3.921
5.210 5.415 5.940 5.797 6.202 5.415 5.940 5.797 6.202 ns
5.845 6.055 6.644 6.472 6.959 6.055 6.644 6.472 6.959 ns
8mA
GCLK t_co
GCLK
PLL ^tco
3.522
3.921
3.522
3.921
5.167 5.362 5.871 5.728 6.133 5.362 5.871 5.728 6.133 ns
5.802 6.002 6.575 6.403 6.890 6.002 6.575 6.403 6.890 ns
SSTL-2
CLASS I
GCLK t_co
10mA _GCLK
PLL ^tco
3.519
3.918
3.519
3.918
5.164 5.359 5.867 5.724 6.129 5.359 5.867 5.724 6.129 ns
5.799 5.999 6.571 6.399 6.886 5.999 6.571 6.399 6.886 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.517
3.916
3.517
3.916
5.164 5.360 5.868 5.725 6.130 5.360 5.868 5.725 6.130 ns
5.799 6.000 6.572 6.400 6.887 6.000 6.572 6.400 6.887 ns
SSTL-2
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.508
3.907
3.508
3.907
5.149 5.344 5.853 5.710 6.115 5.344 5.853 5.710 6.115 ns
5.784 5.984 6.557 6.385 6.872 5.984 6.557 6.385 6.872 ns
4mA
GCLK t_co
GCLK
PLL ^tco
3.529
3.928
3.529
3.928
5.179 5.376 5.887 5.744 6.149 5.376 5.887 5.744 6.149 ns
5.814 6.016 6.591 6.419 6.906 6.016 6.591 6.419 6.906 ns
6mA
GCLK t_co
GCLK
PLL ^tco
3.525
3.924
3.525
3.924
5.177 5.374 5.885 5.742 6.147 5.374 5.885 5.742 6.147 ns
5.812 6.014 6.589 6.417 6.904 6.014 6.589 6.417 6.904 ns
SSTL-18
CLASS I
8mA
GCLK t_co
GCLK
PLL ^tco
3.514
3.913
3.514
3.913
5.167 5.365 5.876 5.733 6.138 5.365 5.876 5.733 6.138 ns
5.802 6.005 6.580 6.408 6.895 6.005 6.580 6.408 6.895 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.503
3.902
3.503
3.902
5.154 5.352 5.863 5.720 6.125 5.352 5.863 5.720 6.125 ns
5.789 5.992 6.567 6.395 6.882 5.992 6.567 6.395 6.882 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.503
3.902
3.503
3.902
5.154 5.352 5.863 5.720 6.125 5.352 5.863 5.720 6.125 ns
5.789 5.992 6.567 6.395 6.882 5.992 6.567 6.395 6.882 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2