EP3SE110F1152I3N Datasheet, PDF (195/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–185
Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part 6 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 3.544
4mA
GCLK
PLL ^tco
4.108
3.544
4.108
5.223 5.415 5.942 5.794 6.223 5.415 5.942 5.794 6.223 ns
6.064 6.263 6.897 6.717 7.260 6.263 6.897 6.717 7.260 ns
GCLK t_co 3.537
6mA
GCLK
PLL ^tco
4.102
3.537
4.102
5.221 5.414 5.941 5.793 6.222 5.414 5.941 5.793 6.222 ns
6.063 6.263 6.903 6.724 7.265 6.263 6.903 6.724 7.265 ns
1.8-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
3.529
4.094
3.529
4.094
5.214 5.406 5.934 5.786 6.215 5.406 5.934 5.786 6.215 ns
6.055 6.255 6.885 6.706 7.247 6.255 6.885 6.706 7.247 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.532
4.096
3.532
4.096
5.217 5.410 5.938 5.790 6.219 5.410 5.938 5.790 6.219 ns
6.058 6.258 6.887 6.707 7.250 6.258 6.887 6.707 7.250 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.529
4.093
3.529
4.093
5.219 5.413 5.942 5.794 6.223 5.413 5.942 5.794 6.223 ns
6.060 6.261 6.895 6.716 7.257 6.261 6.895 6.716 7.257 ns
1.8-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.537
4.101
3.537
4.101
5.218 5.411 5.938 5.790 6.219 5.411 5.938 5.790 6.219 ns
6.059 6.259 6.898 6.718 7.261 6.259 6.898 6.718 7.261 ns
GCLK t_co 3.549
4mA
GCLK
PLL ^tco
4.113
3.549
4.113
5.232 5.425 5.953 5.805 6.234 5.425 5.953 5.805 6.234 ns
6.072 6.273 6.910 6.730 7.273 6.273 6.910 6.730 7.273 ns
GCLK t_co 3.545
6mA
GCLK
PLL ^tco
4.109
3.545
4.109
5.233 5.427 5.956 5.808 6.237 5.427 5.956 5.808 6.237 ns
6.075 6.276 6.907 6.727 7.270 6.276 6.907 6.727 7.270 ns
1.5-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
3.541
4.105
3.541
4.105
5.228 5.422 5.951 5.803 6.232 5.422 5.951 5.803 6.232 ns
6.070 6.271 6.902 6.722 7.265 6.271 6.902 6.722 7.265 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.534
4.098
3.534
4.098
5.221 5.415 5.944 5.796 6.225 5.415 5.944 5.796 6.225 ns
6.063 6.264 6.896 6.716 7.259 6.264 6.896 6.716 7.259 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.535
4.098
3.535
4.098
5.228 5.423 5.954 5.806 6.235 5.423 5.954 5.806 6.235 ns
6.069 6.271 6.900 6.721 7.262 6.271 6.900 6.721 7.262 ns
1.5-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.533
4.096
3.533
4.096
5.209 5.401 5.928 5.780 6.209 5.401 5.928 5.780 6.209 ns
6.050 6.249 6.884 6.704 7.247 6.249 6.884 6.704 7.247 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2