EP3SE110F1152I3N Datasheet, PDF (303/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–293
Table 1–133. EP3SE260 Column Pins Output Timing Parameters (Part 6 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
4mA _GCLK
PLL ^tco
3.483
3.926
3.516
3.915
5.153 5.316 5.910 5.696 6.118 5.316 5.910 5.696 6.118 ns
5.788 6.000 6.560 6.388 6.959 6.000 6.560 6.388 6.959 ns
GCLK t_co
6mA _GCLK
PLL ^tco
3.476
3.919
3.509
3.908
5.151 5.314 5.906 5.695 6.117 5.314 5.906 5.695 6.117 ns
5.786 5.998 6.559 6.387 6.954 5.998 6.559 6.387 6.954 ns
1.8-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
3.468
3.911
3.501
3.900
5.143 5.307 5.879 5.688 6.110 5.307 5.879 5.688 6.110 ns
5.778 5.991 6.552 6.380 6.928 5.991 6.552 6.380 6.928 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.471
3.914
3.504
3.903
5.146 5.310 5.882 5.692 6.114 5.310 5.882 5.692 6.114 ns
5.781 5.994 6.556 6.384 6.931 5.994 6.556 6.384 6.931 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.468
3.911
3.501
3.900
5.149 5.314 5.881 5.696 6.118 5.314 5.881 5.696 6.118 ns
5.784 5.998 6.560 6.388 6.929 5.998 6.560 6.388 6.929 ns
1.8-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.476
3.919
3.509
3.908
5.148 5.311 5.878 5.692 6.114 5.311 5.878 5.692 6.114 ns
5.783 5.995 6.556 6.384 6.927 5.995 6.556 6.384 6.927 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.488
3.931
3.521
3.920
5.161 5.326 5.926 5.707 6.129 5.326 5.926 5.707 6.129 ns
5.796 6.010 6.571 6.399 6.975 6.010 6.571 6.399 6.975 ns
GCLK t_co
6mA _GCLK
PLL ^tco
3.484
3.927
3.517
3.916
5.162 5.327 5.915 5.710 6.132 5.327 5.915 5.710 6.132 ns
5.797 6.011 6.574 6.402 6.964 6.011 6.574 6.402 6.964 ns
1.5-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
3.480
3.923
3.513
3.912
5.158 5.323 5.909 5.705 6.127 5.323 5.909 5.705 6.127 ns
5.793 6.007 6.569 6.397 6.958 6.007 6.569 6.397 6.958 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.473
3.916
3.506
3.905
5.151 5.316 5.896 5.698 6.120 5.316 5.896 5.698 6.120 ns
5.786 6.000 6.562 6.390 6.945 6.000 6.562 6.390 6.945 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.474
3.917
3.507
3.906
5.158 5.324 5.892 5.708 6.130 5.324 5.892 5.708 6.130 ns
5.793 6.008 6.572 6.400 6.941 6.008 6.572 6.400 6.941 ns
1.5-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.472
3.915
3.505
3.904
5.139 5.302 5.871 5.682 6.104 5.302 5.871 5.682 6.104 ns
5.774 5.986 6.546 6.374 6.920 5.986 6.546 6.374 6.920 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2