EP3SE110F1152I3N Datasheet, PDF (285/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–275
Table 1–126. EP3SE110 Row Pins Input Timing Parameters (Part 3 of 3)
I/O Standard
DIFFERENTIAL
2.5-V
SSTL CLASS II
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-0.781
0.907
1.124
-0.861
-0.827
0.969
1.141
-0.861
-1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712 ns
1.379 1.502 1.631 1.568 1.912 1.509 1.636 1.573 1.952 ns
1.827 2.068 2.299 2.178 2.118 2.089 2.323 2.199 2.170 ns
-1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665 ns
Table 1–127 lists the EP3SE110 column pins output timing parameters for differential
I/O standards.
Table 1–127. EP3SE110 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1V
C3
V_CCL=
1.1V
C4
V_CCL=
1.1V
C4L
V_CCL= V_CCL=
1.1V 0.9V
I3
V_CCL=
1.1V
I4
V_CCL=
1.1V
I4L
V_CCL= V_CCL=
1.1V 0.9V
Units
LVDS_E_1R
GCLK t_co 3.152
—
GCLK
PLL
t_co
1.328
3.387
1.502
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 ns
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns
LVDS_E_3R
GCLK t_co 3.148
—
GCLK
PLL
t_co
1.324
3.390
1.505
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 ns
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns
MINI-
LVDS_E_1R
GCLK t_co 3.152
—
GCLK
PLL
t_co
1.328
3.387
1.502
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 ns
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns
MINI-
LVDS_E_3R
GCLK t_co 3.148
—
GCLK
PLL
t_co
1.324
3.390
1.505
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 ns
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns
RSDS_E_1R
GCLK t_co 3.152
—
GCLK
PLL
t_co
1.328
3.387
1.502
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 ns
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns
RSDS_E_3R
GCLK t_co 3.148
—
GCLK
PLL
t_co
1.324
3.390
1.505
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 ns
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2