EP3SE110F1152I3N Datasheet, PDF (299/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–289
Table 1–133. EP3SE260 Column Pins Output Timing Parameters (Part 2 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
4mA _GCLK
PLL ^tco
3.522
3.965
3.555
3.954
5.173 5.328 5.996 5.703 6.123 5.328 5.996 5.703 6.123 ns
5.808 6.012 6.566 6.395 7.044 6.012 6.566 6.395 7.044 ns
3.0-V
LVCMOS
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.443
3.886
3.438
3.881
3.476
3.875
3.471
3.870
5.049 5.199 5.814 5.568 5.988 5.199 5.814 5.568 5.988 ns
5.684 5.883 6.431 6.260 6.862 5.883 6.431 6.260 6.862 ns
5.042 5.192 5.746 5.558 5.980 5.192 5.746 5.558 5.980 ns
5.677 5.876 6.422 6.250 6.795 5.876 6.422 6.250 6.795 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.429
3.872
3.462
3.861
5.028 5.177 5.744 5.543 5.965 5.177 5.744 5.543 5.965 ns
5.663 5.861 6.407 6.235 6.792 5.861 6.407 6.235 6.792 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.644
4.087
3.677
4.076
5.380 5.555 6.278 5.950 6.370 5.555 6.278 5.950 6.370 ns
6.015 6.239 6.813 6.642 7.326 6.239 6.813 6.642 7.326 ns
GCLK t_co 3.544
3.577 5.261 5.429 6.081 5.818 6.238 5.429 6.081 5.818 6.238 ns
8mA _GCLK
PLL ^tco
3.987
3.976 5.896 6.113 6.681 6.510 7.129 6.113 6.681 6.510 7.129 ns
2.5 V
GCLK t_co 3.500
3.533 5.174 5.338 5.941 5.721 6.143 5.338 5.941 5.721 6.143 ns
12mA _GCLK
PLL ^tco
3.943
3.932 5.809 6.022 6.585 6.413 6.989 6.022 6.585 6.413 6.989 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.462
3.905
3.495
3.894
5.135 5.296 5.891 5.678 6.100 5.296 5.891 5.678 6.100 ns
5.770 5.980 6.542 6.370 6.939 5.980 6.542 6.370 6.939 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2