EP3SE110F1152I3N Datasheet, PDF (215/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–205
Table 1–101. EP3SE50 Column Pins Input Timing Parameters (Part 4 of 4)
I/O
Standard
3.0-V |
PCI-X
Clock
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
-0.754
-0.753 -1.062 -1.167 -1.373 -1.328 -1.604 -1.167 -1.373 -1.328 -1.604 ns
0.881
0.880 1.240 1.368 1.594 1.537 1.814 1.368 1.594 1.537 1.814 ns
-1.048
-1.048 -1.465 -1.595 -1.829 -1.771 -2.037 -1.595 -1.829 -1.771 -2.037 ns
1.301
1.301 1.835 2.011 2.291 2.206 2.483 2.011 2.291 2.206 2.483 ns
Table 1–102 lists the EP3SE50 row pins input timing parameters for single-ended I/O
standards.
Table 1–102. EP3SE50 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
t_su
GCLK
t_h
3.3-V LVTTL
GCLK ^tsu
PLL _th
3.3-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
t_su
GCLK
3.0-V LVTTL
t_h
GCLK ^tsu
PLL _th
3.0-V
LVCMOS
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
2.5 V
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
1.8 V
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
-0.896
-0.926 -1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 ns
1.009
1.052 1.597 1.816 1.931 1.813 1.843 1.809 1.936 1.818 1.895 ns
0.952
0.960 1.494 1.640 1.888 1.819 2.111 1.667 1.903 1.836 2.144 ns
-0.703
-0.700 -1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 ns
-0.896
-0.926 -1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 ns
1.009
1.052 1.597 1.816 1.931 1.813 1.843 1.809 1.936 1.818 1.895 ns
0.952
0.960 1.494 1.640 1.888 1.819 2.111 1.667 1.903 1.836 2.144 ns
-0.703
-0.700 -1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 ns
-0.902
-0.937 1.491 1.641 1.891 1.822 2.114 1.666 1.908 1.841 2.149 ns
1.015
1.063 -1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 ns
0.946
0.949 1.600 1.815 1.928 1.810 1.840 1.810 1.931 1.813 1.890 ns
-0.697
-0.689 1.491 1.641 1.891 1.822 2.114 1.666 1.908 1.841 2.149 ns
-0.902
-0.937 1.500 1.654 1.906 1.837 2.129 1.675 1.918 1.851 2.159 ns
1.015
1.063 -1.317 -1.447 -1.676 -1.623 -1.914 -1.459 -1.678 -1.627 -1.942 ns
0.946
0.949 1.591 1.802 1.913 1.795 1.825 1.801 1.921 1.803 1.880 ns
-0.697
-0.689 1.500 1.654 1.906 1.837 2.129 1.675 1.918 1.851 2.159 ns
-0.890
-0.930 1.510 1.730 1.876 1.758 1.788 1.729 1.881 1.762 1.840 ns
1.003
1.056 1.458 1.596 1.807 1.742 2.015 1.614 1.817 1.754 2.048 ns
0.958
0.956 -1.272 -1.388 -1.573 -1.523 -1.797 -1.395 -1.573 -1.526 -1.829 ns
-0.709
-0.696 1.510 1.730 1.876 1.758 1.788 1.729 1.881 1.762 1.840 ns
-0.869
-0.907 1.534 1.762 1.944 1.826 1.856 1.760 1.946 1.827 1.905 ns
0.890
0.886 1.434 1.564 1.739 1.674 1.947 1.583 1.752 1.689 1.983 ns
0.986
1.035 -1.248 -1.356 -1.505 -1.455 -1.729 -1.364 -1.508 -1.461 -1.764 ns
-0.859
-0.896 1.613 1.863 2.103 1.985 2.015 1.856 2.101 1.982 2.060 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2