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EP3SE110F1152I3N Datasheet, PDF (115/341 Pages) Altera Corporation – Stratix III Device Handbook
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–105
Table 1–64 lists the EP3SL110 row pins output timing parameters for single-ended I/O
standards.
Table 1–64. EP3SL110 Row Pins Output Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
Fast Model
Industrial Commercial
C2 C3
VCCL= VCCL=
1.1 V 1.1 V
C4
VCCL=
1.1 V
C4L
VCCL= VCCL=
1.1 V 0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL= VCCL=
1.1 V 0.9 V
Units
4mA
GCLK tco
GCLK
PLL
tco
3.182
1.457
3.481
1.650
4.833 5.216 5.678 5.579 5.814 5.256 5.802 5.703 5.896 ns
2.051 2.136 2.329 2.349 2.337 2.239 2.435 2.454 2.331 ns
3.3-V
LVTTL
8mA
GCLK tco
GCLK
PLL
tco
3.116
1.364
3.376
1.545
4.703 5.078 5.533 5.434 5.669 5.143 5.653 5.554 5.747 ns
1.921 1.998 2.184 2.204 2.192 2.098 2.286 2.305 2.182 ns
GCLK tco
12mA
GCLK
PLL
tco
3.037
1.265
3.270
1.439
4.584 4.955 5.405 5.306 5.541 5.044 5.521 5.422 5.615 ns
1.802 1.875 2.056 2.076 2.064 1.971 2.154 2.173 2.050 ns
4mA
3.3-V
LVCMOS
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
3.184
1.467
3.041
1.269
3.485
1.654
3.276
1.445
4.841 5.221 5.682 5.583 5.818 5.264 5.806 5.707 5.900 ns
2.059 2.141 2.333 2.353 2.341 2.245 2.439 2.458 2.335 ns
4.590 4.961 5.411 5.312 5.548 5.056 5.528 5.429 5.622 ns
1.808 1.881 2.062 2.082 2.070 1.977 2.161 2.180 2.057 ns
4mA
GCLK tco
GCLK
PLL
tco
3.143
1.411
3.427
1.596
4.785 5.169 5.634 5.535 5.770 5.224 5.760 5.661 5.854 ns
2.003 2.089 2.285 2.305 2.293 2.196 2.393 2.412 2.289 ns
3.0-V
LVTTL
8mA
GCLK tco
GCLK
PLL
tco
3.042
1.286
3.300
1.469
4.632 5.010 5.470 5.371 5.606 5.082 5.596 5.496 5.689 ns
1.850 1.930 2.121 2.141 2.129 2.034 2.229 2.247 2.124 ns
GCLK tco
12mA
GCLK
PLL
tco
3.005
1.247
3.249
1.418
4.550 4.927 5.382 5.283 5.518 5.014 5.503 5.403 5.596 ns
1.768 1.847 2.033 2.053 2.041 1.948 2.136 2.154 2.031 ns
3.0-V
LVCMOS
4mA
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
3.064
1.325
2.992
1.225
3.346
1.515
3.227
1.396
4.679 5.062 5.524 5.425 5.660 5.115 5.649 5.549 5.742 ns
1.897 1.982 2.175 2.195 2.183 2.088 2.282 2.300 2.177 ns
4.515 4.888 5.343 5.244 5.479 4.984 5.463 5.363 5.556 ns
1.733 1.808 1.994 2.014 2.002 1.908 2.096 2.114 1.991 ns
4mA
GCLK tco
GCLK
PLL
tco
3.169
1.437
3.463
1.632
4.917 5.323 5.806 5.707 5.942 5.356 5.939 5.839 6.032 ns
2.135 2.243 2.457 2.477 2.465 2.356 2.572 2.590 2.467 ns
2.5 V
8mA
GCLK tco
GCLK
PLL
tco
3.084
1.327
3.365
1.534
4.762 5.160 5.636 5.537 5.772 5.219 5.765 5.665 5.858 ns
1.980 2.080 2.287 2.307 2.295 2.189 2.398 2.416 2.293 ns
GCLK tco
12mA
GCLK
PLL
tco
3.027
1.281
3.288
1.457
4.651 5.041 5.510 5.411 5.646 5.130 5.635 5.535 5.728 ns
1.869 1.961 2.161 2.181 2.169 2.066 2.268 2.286 2.163 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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