EP3SE110F1152I3N Datasheet, PDF (122/341 Pages) Altera Corporation – Stratix III Device Handbook

1–112
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–66. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3)
I/O Standard Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su
DIFFERENTIAL ^GCLK _th
1.5-V
SSTL CLASS II GCLK ^tsu
PLL _th
DIFFERENTIAL
GCLK
t_su
t_h
1.8-V
SSTL CLASS I GCLK ^tsu
PLL _th
t_su
DIFFERENTIAL ^GCLK
1.8-V
t_h
SSTL CLASS II GCLK ^tsu
PLL _th
t_su
DIFFERENTIAL ^GCLK _th
2.5-V
SSTL CLASS I GCLK ^tsu
PLL _th
DIFFERENTIAL
GCLK
t_su
t_h
2.5-V
SSTL CLASS II GCLK ^tsu
PLL _th
-0.733
0.850
1.145
-0.891
-0.747
0.864
1.131
-0.877
-0.747
0.864
1.131
-0.877
-0.756
0.873
1.122
-0.868
-0.756
0.873
1.122
-0.868
-0.777
0.910
1.160
-0.890
-0.789
0.922
1.148
-0.878
-0.789
0.922
1.148
-0.878
-0.798
0.931
1.139
-0.869
-0.798
0.931
1.139
-0.869
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642 ns
1.311 1.430 1.551 1.490 1.818 1.438 1.559 1.499 1.862 ns
1.853 2.090 2.322 2.203 2.139 2.108 2.344 2.222 2.187 ns
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702 ns
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659 ns
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879 ns
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170 ns
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685 ns
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659 ns
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879 ns
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170 ns
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685 ns
-1.145 -1.241 -1.345 -1.296 -1.623 -1.238 -1.337 -1.291 -1.661 ns
1.336 1.454 1.579 1.518 1.847 1.459 1.582 1.521 1.886 ns
1.825 2.064 2.293 2.173 2.110 2.086 2.321 2.197 2.163 ns
-1.422 -1.611 -1.789 -1.698 -1.625 -1.623 -1.805 -1.711 -1.674 ns
-1.145 -1.241 -1.345 -1.296 -1.623 -1.238 -1.337 -1.291 -1.661 ns
1.336 1.454 1.579 1.518 1.847 1.459 1.582 1.521 1.886 ns
1.825 2.064 2.293 2.173 2.110 2.086 2.321 2.197 2.163 ns
-1.422 -1.611 -1.789 -1.698 -1.625 -1.623 -1.805 -1.711 -1.674 ns
Table 1–67 lists the EP3SL110 column pins output timing parameters for differential
I/O standards.
Table 1–67. EP3SL110 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
LVDS_E_1R
LVDS_E_3R
MINI-
LVDS_E_1R
MINI-
LVDS_E_3R
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
—
GCLK
PLL
t_co
3.100
1.308
3.330
1.480
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 ns
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 ns
GCLK t_co
—
GCLK
PLL
t_co
3.096
1.304
3.333
1.483
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 ns
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 ns
GCLK t_co
—
GCLK
PLL
t_co
3.100
1.308
3.330
1.480
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 ns
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 ns
GCLK t_co
—
GCLK
PLL
t_co
3.096
1.304
3.333
1.483
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 ns
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation