EP3SE110F1152I3N Datasheet, PDF (196/341 Pages) Altera Corporation – Stratix III Device Handbook

1–186
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part 7 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 3.552
4mA
GCLK
PLL ^tco
4.117
3.552
4.117
5.246 5.442 5.974 5.826 6.255 5.442 5.974 5.826 6.255 ns
6.087 6.291 6.929 6.749 7.292 6.291 6.929 6.749 7.292 ns
GCLK t_co 3.544
6mA
GCLK
PLL ^tco
4.108
3.544
4.108
5.237 5.433 5.965 5.817 6.246 5.433 5.965 5.817 6.246 ns
6.078 6.282 6.917 6.737 7.280 6.282 6.917 6.737 7.280 ns
1.2-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
3.545
4.108
3.545
4.108
5.244 5.442 5.974 5.826 6.255 5.442 5.974 5.826 6.255 ns
6.085 6.290 6.920 6.740 7.283 6.290 6.920 6.740 7.283 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.534
4.098
3.534
4.098
5.231 5.428 5.960 5.812 6.241 5.428 5.960 5.812 6.241 ns
6.072 6.276 6.915 6.736 7.277 6.276 6.915 6.736 7.277 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.534
4.098
3.534
4.098
5.231 5.428 5.961 5.813 6.242 5.428 5.961 5.813 6.242 ns
6.073 6.277 6.906 6.727 7.269 6.277 6.906 6.727 7.269 ns
1.2-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.555
4.119
3.555
4.119
5.247 5.443 5.974 5.826 6.255 5.443 5.974 5.826 6.255 ns
6.089 6.292 6.943 6.763 7.306 6.292 6.943 6.763 7.306 ns
3.0-V PCI —
GCLK t_co
GCLK
PLL ^tco
3.658
4.222
3.658
4.222
5.292 5.477 5.999 5.851 6.280 5.477 5.999 5.851 6.280 ns
6.134 6.328 6.974 6.794 7.337 6.328 6.974 6.794 7.337 ns
3.0-V
PCI-X
GCLK t_co 3.658
—
GCLK
PLL ^tco
4.222
3.658
4.222
5.292 5.477 5.999 5.851 6.280 5.477 5.999 5.851 6.280 ns
6.134 6.328 6.974 6.794 7.337 6.328 6.974 6.794 7.337 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation