EP3SE110F1152I3N Datasheet, PDF (162/341 Pages) Altera Corporation – Stratix III Device Handbook

1–152
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–83 lists the EP3SL200 column pins output timing parameters for single-ended
I/O standards.
Table 1–83. EP3SL200 Column Pins Output Timing Parameters (Part 1 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
4mA
GCLK t_co
GCLK
PLL ^tco
3.677
4.076
3.677
4.076
5.302 5.492 5.997 5.854 6.259 5.492 5.997 5.854 6.259 ns
5.937 6.132 6.701 6.529 7.016 6.132 6.701 6.529 7.016 ns
3.3-V
LVTTL
8mA
GCLK t_co
GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.610
4.009
3.524
3.923
3.610
4.009
3.524
3.923
5.193 5.381 5.884 5.741 6.146 5.381 5.884 5.741 6.146 ns
5.828 6.021 6.588 6.416 6.903 6.021 6.588 6.416 6.903 ns
5.089 5.282 5.792 5.649 6.054 5.282 5.792 5.649 6.054 ns
5.724 5.922 6.496 6.324 6.811 5.922 6.496 6.324 6.811 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.517
3.916
3.517
3.916
5.072 5.254 5.751 5.608 6.013 5.254 5.751 5.608 6.013 ns
5.707 5.894 6.455 6.283 6.770 5.894 6.455 6.283 6.770 ns
4mA
GCLK t_co
GCLK
PLL ^tco
3.683
4.082
3.683
4.082
5.306 5.497 6.004 5.861 6.266 5.497 6.004 5.861 6.266 ns
5.941 6.137 6.708 6.536 7.023 6.137 6.708 6.536 7.023 ns
3.3-V
LVCMOS
8mA
GCLK t_co
GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.528
3.927
3.535
3.934
3.528
3.927
3.535
3.934
5.099 5.299 5.803 5.660 6.065 5.299 5.803 5.660 6.065 ns
5.734 5.939 6.507 6.335 6.822 5.939 6.507 6.335 6.822 ns
5.093 5.278 5.777 5.634 6.039 5.278 5.777 5.634 6.039 ns
5.728 5.918 6.481 6.309 6.796 5.918 6.481 6.309 6.796 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.519
3.918
3.519
3.918
5.071 5.253 5.748 5.605 6.010 5.253 5.748 5.605 6.010 ns
5.706 5.893 6.452 6.280 6.767 5.893 6.452 6.280 6.767 ns
4mA
GCLK t_co
GCLK
PLL ^tco
3.641
4.040
3.641
4.040
5.269 5.460 5.964 5.821 6.226 5.460 5.964 5.821 6.226 ns
5.904 6.100 6.668 6.496 6.983 6.100 6.668 6.496 6.983 ns
3.0-V
LVTTL
8mA
GCLK t_co
GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.530
3.929
3.494
3.893
3.530
3.929
3.494
3.893
5.139 5.326 5.826 5.684 6.088 5.326 5.826 5.684 6.088 ns
5.774 5.966 6.531 6.360 6.845 5.966 6.531 6.360 6.845 ns
5.076 5.257 5.752 5.610 6.014 5.257 5.752 5.610 6.014 ns
5.711 5.897 6.457 6.286 6.771 5.897 6.457 6.286 6.771 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.476
3.875
3.476
3.875
5.047 5.229 5.724 5.581 5.986 5.229 5.724 5.581 5.986 ns
5.682 5.869 6.428 6.256 6.743 5.869 6.428 6.256 6.743 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation