EP3SE110F1152I3N Datasheet, PDF (330/341 Pages) Altera Corporation – Stratix III Device Handbook

1–320
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–180 and Table 1–181 list the regional clock timing parameters for EP3SE50
devices.
Table 1–180. EP3SE50 Column Pin Regional Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
C2
C3
C4
C4L
Industrial
1.711
1.711
0.034
0.106
Commercial
1.721
1.721
0.038
0.102
V_CCL=
1.1 V
V_CCL=
1.1 V
2.429 2.679
2.429 2.679
-0.193 -0.255
-0.074 -0.101
V_CCL=
1.1 V
3.053
3.053
-0.212
-0.212
V_CCL=
1.1 V
2.767
2.767
-0.168
-0.168
V_CCL=
0.9 V
3.191
3.191
0.040
0.040
I3
V_CCL=
1.1 V
2.679
2.679
-0.255
-0.101
I4
V_CCL=
1.1 V
3.053
3.053
0.263
0.263
I4L
V_CCL=
1.1 V
2.767
2.767
-0.168
-0.168
V_CCL=
0.9 V
3.191
3.191
0.040
0.040
Units
ns
ns
ns
ns
Table 1–181. EP3SE50 Row Pin Regional Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial Commercial
1.640
1.558
0.020
-0.062
1.732
1.641
0.091
0.000
C2
C3
C4
V_CCL=
1.1 V
V_CCL=
1.1 V
V_CCL=
1.1 V
2.361 2.580 2.905
2.219 2.417 2.724
-0.168 -0.241 -0.208
-0.310 -0.404 -0.389
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.810 2.977
2.639 2.818
-0.155 -0.210
-0.326 -0.369
I3
V_CCL=
1.1 V
2.636
2.466
-0.191
-0.361
I4
V_CCL=
1.1 V
2.960
2.771
0.321
0.132
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.868 3.003
2.689 2.844
-0.108 -0.264
-0.287 -0.423
Units
ns
ns
ns
ns
Table 1–182 and Table 1–183 list the periphery clock timing parameters for EP3SE50
devices.
Table 1–182. EP3SE50 Column Pin Periphery Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial
1.472
1.472
-0.047
-0.047
Commercial
1.481
1.481
-0.044
-0.044
C2
C3
C4
V_CCL=
1.1 V
V_CCL=
1.1 V
V_CCL=
1.1 V
2.155 2.417 2.825
2.155 2.417 2.825
-0.288 -0.347 -0.302
-0.288 -0.347 -0.302
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.681 3.247
2.681 3.247
-0.266 -0.079
-0.266 -0.079
I3
V_CCL=
1.1 V
2.417
2.417
-0.347
-0.347
I4
V_CCL=
1.1 V
2.819
2.819
0.300
0.300
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.681 3.247
2.681 3.247
-0.266 -0.079
-0.266 -0.079
Units
ns
ns
ns
ns
Table 1–183. EP3SE50 Row Pin Periphery Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial Commercial
1.467
1.385
-0.021
-0.103
1.543
1.452
0.036
-0.055
C2
C3
C4
V_CCL=
1.1 V
V_CCL=
1.1 V
V_CCL=
1.1 V
2.208 2.472 2.843
2.063 2.309 2.662
-0.231 -0.307 -0.282
-0.373 -0.470 -0.463
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.729 3.012
2.558 2.853
-0.230 -0.301
-0.401 -0.460
I3
V_CCL=
1.1 V
2.521
2.351
-0.262
-0.432
I4
V_CCL=
1.1 V
2.891
2.702
0.372
0.183
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.771 3.028
2.592 2.869
-0.184 -0.361
-0.363 -0.520
Units
ns
ns
ns
ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation