EP3SE110F1152I3N Datasheet, PDF (37/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
1–27
Table 1–29. Transmitter Channel-to-Channel Skew (TCCS)—Write Side (Note 1) (Part 1 of 2)
C2
C3, I3
C4, I4
Memory Type
I/O
Standard
Width
V_CCL = 1.1 V
TCCS (ps)
V_CCL = 1.1 V
TCCS (ps)
V_CCL = 1.1 V
TCCS (ps)
DDR3 SDRAM (with
Deskew circuitry,
401 MHz–533 MHz)
DDR3 SDRAM (8-tap
phase offset,
375 MHz–400 MHz)
DDR3 SDRAM (8-tap
phase offset,
360 MHz–375 MHz)
DDR3 SDRAM (10-tap
phase offset,
333 MHz–360 MHz)
DDR3 SDRAM (10-tap
phase offset,
300 MHz–333 MHz)
DDR3 SDRAM
(Non-leveling interface)
DDR2 SDRAM Differential
DQS
DDR2 SDRAM
Single-ended DQS
DDR SDRAM
Single-ended DQS
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation (2)
1.5-V
SSTL
1.5-V
SSTL
1.5-V
SSTL
1.5-V
SSTL
1.5-V
SSTL
1.5-V
SSTL
1.8-V
SSTL
1.8-V
SSTL
2.5-V
SSTL
1.5-V
HSTL
1.5-V
HSTL
Lead Lag Lead Lag Lead Lag
×4, ×8 253 262 — — — —
×4, ×8 293 284 341 332 — —
×4, ×8 293 284 341 373 — —
×4, ×8 169 470 217 496 258 528
×4, ×8 169 470 217 496 258 528
×4, ×8 268 246 230 355 250 388
×4, ×8 229 246 230 355 250 388
×4, ×8 316 168 318 239 346 260
×4, ×8 313 157 315 222 343 242
×9, ×18, 290 278 292 388 315 421
×36
×36
310 298 312 408 335 441
C4L, I4L
V_CCL = 1.1 V
TCCS (ps)
Lead Lag
——
——
——
258 528
258 528
250 388
250 388
346 260
343 242
315 421
335 441
C4L, I4L
V_CCL = 0.9 V
TCCS (ps)
Lead Lag
——
——
——
——
——
250 388
350 488
446 360
443 342
415 521
435 541
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2