EP3SE110F1152I3N Datasheet, PDF (48/341 Pages) Altera Corporation – Stratix III Device Handbook

1–38
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Programmable Output Buffer Delay
Table 1–40 lists the delay chain settings that control the rising and falling edge delays
of the output buffer. The default delay is 0 ps.
Table 1–40. Programmable Output Buffer Delay (Note 1)
Symbol
Parameter
Typical
Unit
0 (default)
ps
D_OUTBUF
Rising and/or Falling
50
Edge delay
100
ps
ps
150
ps
Note to Table 1–40:
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
Control assignment to either positive, negative, or both edges with the specific values stated in this table for the
Output Buffer Delay assignment.
User I/O Pin Timing
Table 1–41 through Table 1–140 list user I/O pin timing for Stratix III devices. I/O
buffer t_su, t_h, and t_co are reported for the cases when the I/O clock is driven by a
non-PLL global clock (GCLK) and the PLL is driven by the global clock (GCLK-PLL).
For t_su, t_h, and t_co using the regional clock, add the value from the adder tables listed
for each device to the GCLK/GCLK-PLL values for the device.
EP3SL50 I/O Timing Parameters
Table 1–41 through Table 1–44 list the maximum I/O timing parameters for EP3SL50
devices for single-ended I/O standards.
Table 1–41 lists the EP3SL50 column pins input timing parameters for single-ended
I/O standards.
Table 1–41. EP3SL50 Column Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
3.3-V
LVTTL
3.3-V
LVCMOS
3.0-V
LVTTL
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-0.690
0.816
-0.975
1.226
-0.690
0.816
-0.975
1.226
-0.701
0.827
-0.986
1.237
-0.689
0.814
-0.975
1.226
-0.689
0.814
-0.975
1.226
-0.700
0.825
-0.986
1.237
-1.004 -1.103 -1.311 -1.266 -1.627 -1.103 -1.311 -1.266 -1.627 ns
1.182 1.304 1.531 1.475 1.830 1.304 1.531 1.475 1.830 ns
-1.405 -1.532 -1.773 -1.713 -2.026 -1.532 -1.773 -1.713 -2.026 ns
1.774 1.947 2.232 2.148 2.471 1.947 2.232 2.148 2.471 ns
-1.004 -1.103 -1.311 -1.266 -1.627 -1.103 -1.311 -1.266 -1.627 ns
1.182 1.304 1.531 1.475 1.830 1.304 1.531 1.475 1.830 ns
-1.405 -1.532 -1.773 -1.713 -2.026 -1.532 -1.773 -1.713 -2.026 ns
1.774 1.947 2.232 2.148 2.471 1.947 2.232 2.148 2.471 ns
-1.003 -1.105 -1.310 -1.265 -1.626 -1.105 -1.310 -1.265 -1.626 ns
1.181 1.306 1.530 1.474 1.829 1.306 1.530 1.474 1.829 ns
-1.404 -1.534 -1.772 -1.712 -2.025 -1.534 -1.772 -1.712 -2.025 ns
1.773 1.949 2.231 2.147 2.470 1.949 2.231 2.147 2.470 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation