EP3SE110F1152I3N Datasheet, PDF (272/341 Pages) Altera Corporation – Stratix III Device Handbook

1–262
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–123. EP3SE110 Column Pins Output Timing Parameters (Part 2 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
V_CCL=
1.1 V 0.9 V
UnitS
GCLK t_co
4mA
GCLK
PLL
t_co
3.367
3.748
3.367
3.759
4.701 5.081 5.550 5.416 5.726 5.081 5.550 5.416 5.726 ns
5.286 5.707 6.307 6.144 6.544 5.707 6.307 6.144 6.544 ns
3.0-V
LVCMOS
GCLK t_co
8mA
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
3.288
3.669
3.283
3.662
3.288
3.680
3.283
3.675
4.577 4.952 5.415 5.281 5.591 4.952 5.415 5.281 5.591 ns
5.163 5.577 6.172 6.009 6.413 5.577 6.172 6.009 6.413 ns
4.570 4.945 5.407 5.272 5.584 4.945 5.407 5.272 5.584 ns
5.155 5.570 6.163 5.999 6.401 5.570 6.163 5.999 6.401 ns
GCLK t_co
16mA
GCLK
PLL
t_co
3.274
3.653
3.274
3.666
4.556 4.930 5.392 5.257 5.569 4.930 5.392 5.257 5.569 ns
5.141 5.554 6.148 5.984 6.387 5.554 6.148 5.984 6.387 ns
GCLK t_co
4mA
GCLK
PLL
t_co
3.489
3.868
3.489
3.881
4.908 5.308 5.797 5.663 5.974 5.308 5.797 5.663 5.974 ns
5.493 5.932 6.554 6.391 6.791 5.932 6.554 6.391 6.791 ns
GCLK t_co 3.389
3.389 4.789 5.182 5.665 5.531 5.841 5.182 5.665 5.531 5.841 ns
8mA
GCLK
PLL
t_co
3.771
3.781 5.374 5.807 6.422 6.259 6.659 5.807 6.422 6.259 6.659 ns
2.5 V
GCLK t_co 3.345
3.345 4.702 5.091 5.570 5.435 5.747 5.091 5.570 5.435 5.747 ns
12mA
GCLK
PLL
t_co
3.726
3.737 5.287 5.716 6.326 6.162 6.564 5.716 6.326 6.162 6.564 ns
GCLK t_co
16mA
GCLK
PLL
t_co
3.307
3.687
3.307
3.699
4.663 5.049 5.527 5.392 5.704 5.049 5.527 5.392 5.704 ns
5.248 5.674 6.283 6.119 6.521 5.674 6.283 6.119 6.521 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation