EP3SE110F1152I3N Datasheet, PDF (43/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–33
5. Compare the results of steps 2 and 4. The increase or decrease in delay must be
added to or subtracted from the I/O Standard Output Adder delays to yield the
actual worst-case propagation delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions listed in Table 1–37
using Equation 1–1 on page 1–7. Figure 1–6 shows the circuit that is represented by
the output timing of the Quartus II software.
Figure 1–6. Output Delay Timing Report Setup for Single-Ended Outputs and Dedicated Differential
Outputs (Note 1)
V_CCIO
Output
Buffer
Output
V_MEAS
V_TT
R_T
R_S
C_L
Output_p
R_D
Output_n
GND
GND
Note to Figure 1–6:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay
must be accounted for with IBIS model simulations.
Figure 1–7 and Figure 1–8 show the circuit that is represented by the output timing of
the Quartus II software for differential outputs with single and multiple external
resistors, respectively.
Figure 1–7. Output Delay Timing Report Setup for Differential Outputs with Single External Resistor
Non-Dedicated
Differential Outputs
V_MEAS
V_MEAS
R_P
R_D
Figure 1–8. Output Delay Timing Report Setup for Differential Outputs with Three External Resistor
Non-Dedicated
Differential Outputs
V_MEAS R_S
R_P
R_D
V_MEAS
R_S
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2