EP3SE110F1152I3N Datasheet, PDF (103/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–93
Table 1–60 lists the EP3SL70 row pin delay adders when using the regional clock.
Table 1–60. EP3SL70 Row Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.111
0.099
-0.113
-0.107
0.123
0.105
-0.127
-0.112
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.177 0.192 0.207 0.198 0.263 0.194 0.212 0.201 0.266 ns
0.156 0.175 0.195 0.185 0.263 0.177 0.195 0.188 0.263 ns
-0.183 -0.198 -0.213 -0.205 -0.272 -0.202 -0.216 -0.21 -0.273 ns
-0.164 -0.185 -0.202 -0.193 -0.258 -0.184 -0.204 -0.197 -0.257 ns
EP3SL110 I/O Timing Parameters
Table 1–61 through Table 1–65 list the maximum I/O timing parameters for EP3SL110
devices for single-ended I/O standards.
Table 1–61 lists the EP3SL110 column pins input timing parameters for single-ended
I/O standards.
Table 1–61. EP3SL110 Column Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
GCLK ^tsu
t_h
3.3-V LVTTL
GCLK ^tsu
PLL _th
3.3-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
3.0-V LVTTL
GCLK ^tsu
PLL _th
3.0-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
2.5 V
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-0.917
1.053
-1.234
1.512
-0.917
1.053
-1.234
1.512
-0.928
1.064
-1.245
1.523
-0.928
1.064
-1.245
1.523
-0.923
1.059
-1.240
1.518
-0.917
1.053
-1.176
1.460
-0.917
1.053
-1.176
1.460
-0.928
1.064
-1.187
1.471
-0.928
1.064
-1.187
1.471
-0.923
1.059
-1.182
1.466
-1.333 -1.452 -1.682 -1.627 -1.980 -1.452 -1.682 -1.627 -1.980 ns
1.524 1.667 1.918 1.850 2.205 1.667 1.918 1.850 2.205 ns
-1.704 -1.940 -2.210 -2.135 -2.470 -1.940 -2.210 -2.135 -2.470 ns
2.116 2.394 2.710 2.610 2.971 2.394 2.710 2.610 2.971 ns
-1.333 -1.452 -1.682 -1.627 -1.980 -1.452 -1.682 -1.627 -1.980 ns
1.524 1.667 1.918 1.850 2.205 1.667 1.918 1.850 2.205 ns
-1.704 -1.940 -2.210 -2.135 -2.470 -1.940 -2.210 -2.135 -2.470 ns
2.116 2.394 2.710 2.610 2.971 2.394 2.710 2.610 2.971 ns
-1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626 -1.979 ns
1.523 1.669 1.917 1.849 2.204 1.669 1.917 1.849 2.204 ns
-1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134 -2.469 ns
2.115 2.396 2.709 2.609 2.970 2.396 2.709 2.609 2.970 ns
-1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626 -1.979 ns
1.523 1.669 1.917 1.849 2.204 1.669 1.917 1.849 2.204 ns
-1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134 -2.469 ns
2.115 2.396 2.709 2.609 2.970 2.396 2.709 2.609 2.970 ns
-1.341 -1.466 -1.700 -1.645 -1.998 -1.466 -1.700 -1.645 -1.998 ns
1.532 1.681 1.936 1.868 2.223 1.681 1.936 1.868 2.223 ns
-1.712 -1.954 -2.228 -2.153 -2.488 -1.954 -2.228 -2.153 -2.488 ns
2.124 2.408 2.728 2.628 2.989 2.408 2.728 2.628 2.989 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2