EP3SE110F1152I3N Datasheet, PDF (87/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–77
Table 1–53. EP3SL70 Column Pins Output Timing Parameters (Part 7 of 7)
I/O
Standard
Clock
1.2-V
HSTL
CLASS I
1.2-V
HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
GCLK t_co
4mA _GCLK
PLL ^tco
GCLK t_co
6mA _GCLK
PLL ^tco
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
10mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
GCLK t_co
16mA _GCLK
PLL ^tco
GCLK t_co
— _GCLK
PLL ^tco
GCLK t_co
— _GCLK
PLL ^tco
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
3.035
3.035 4.284 4.647 5.117 4.996 5.204 4.647 5.117 4.996 5.204 ns
3.361
3.361 4.768 5.176 5.714 5.571 5.900 5.176 5.714 5.571 5.900 ns
3.026
3.026 4.275 4.638 5.108 4.987 5.195 4.638 5.108 4.987 5.195 ns
3.353
3.353 4.759 5.167 5.705 5.562 5.888 5.167 5.705 5.562 5.888 ns
3.026
3.026 4.282 4.646 5.117 4.996 5.204 4.646 5.117 4.996 5.204 ns
3.354
3.354 4.767 5.175 5.714 5.571 5.891 5.175 5.714 5.571 5.891 ns
3.016
3.016 4.269 4.632 5.103 4.982 5.190 4.632 5.103 4.982 5.190 ns
3.343
3.343 4.754 5.162 5.700 5.557 5.885 5.162 5.700 5.557 5.885 ns
3.016
3.016 4.270 4.633 5.104 4.983 5.191 4.633 5.104 4.983 5.191 ns
3.343
3.343 4.754 5.162 5.701 5.558 5.877 5.162 5.701 5.558 5.877 ns
3.037
3.037 4.286 4.648 5.117 4.996 5.204 4.648 5.117 4.996 5.204 ns
3.364
3.364 4.770 5.177 5.714 5.571 5.914 5.177 5.714 5.571 5.914 ns
3.140
3.140 4.331 4.684 5.142 5.021 5.229 4.684 5.142 5.021 5.229 ns
3.467
3.467 4.815 5.211 5.739 5.596 5.945 5.211 5.739 5.596 5.945 ns
3.140
3.140 4.331 4.684 5.142 5.021 5.229 4.684 5.142 5.021 5.229 ns
3.467
3.467 4.815 5.211 5.739 5.596 5.945 5.211 5.739 5.596 5.945 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2