AK4632 Datasheet, PDF (68/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
3. When an external clock (MCKI pin) is used in PLL Slave Mode.
PMPLL bit
(Addr:01H,D0)
MCKO bit
(Addr:01H,D1)
MCKPD bit
(Addr:01H,D2)
External MCKI
(1)
(1)
(1)
(2)
Input
Example
Audio I/F Format : DSP Mode, BCKP = MSBS = “0”
PLL Reference clock: MCKI
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1) Addr:01H, Data:04H
(2) Stop the external clocks
Figure 58. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
Pull down the MCKI pin: MCKPD bit = “0” → “1”
When the external master clock becomes Hi-Z, MCKI pin should be pulled down.
(2) Stop the external master clock.
4. EXT Slave Mode
MCKPD bit
(Addr:01H,D2)
External MCKI
External BICK
External FCK
(1)
(2)
Input
(2)
Input
(2)
Input
Example
Audio I/F Format :MSB justified(ADC and DAC)
Input MCKI frequency:1024fs
Sampling Frequency:8kHz
(1) Addr:01H, Data:04H
(2) Stop the external clocks
Figure 59. Clock Stopping Sequence (4)
<Example>
(1) Pull down the MCKI pin: MCKPD bit = “0” → “1”
When the external master clock becomes Hi-Z, MCKI pin should be pulled down.
(2) Stop the external MCKI, BICK and FCK clocks.
„ Power down
If the clocks are supplied, power down VCOM (PMVCM bit: “1” → “0”) after all blocks except for VCOM are
powered-down and a master clock stops. The AK4632 is also powered-down by PDN pin = “L”. When PDN pin = “L”,
the registers are initialized.
MS0396-E-00
- 68 -
2005/06