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AK4632 Datasheet, PDF (23/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP | |||
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ASAHI KASEI
[AK4632]
When PLL2 bit is â0â (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3,
FS1-0 bits. (See Table 6)
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range
0
0
Donât care
0
0
7.35kHz ⤠fs ⤠8kHz Default
1
0
Donât care
0
1
8kHz < fs ⤠12kHz
2
0
Donât care
1
0
12kHz < fs ⤠16kHz
3
0
Donât care
1
1
16kHz < fs ⤠24kHz
6
1
Donât care
1
0
24kHz < fs ⤠32kHz
7
1
Donât care
1
1
32kHz < fs ⤠48kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = â0â and PMPLL bit = â1â
 PLL Unlock State
1) PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
In this mode, irregular frequency clocks are output from FCK, BICK and MCKO pins after PMPLL bit = â0â Ã â1â or
sampling frequency is changed. After that PLL is unlocked, BICK and FCK pins output âLâ for a moment, and invalid
frequency clock is output from MCKO pin at MCKO bit = â1â. If MCKO bit is â0â, MCKO pin is output to âLâ. (See
Table 7)
After the PLL is locked, a first period of FCK and BICK may be invalid clock, but these clocks return to normal state after
a period of 1/fs.
PLL State
MCKO pin
MCKO bit = â0â MCKO bit = â1â
After that PMPLL bit â0â Ã â1â âLâ Output
Invalid
BICK pin
Invalid
FCK pin
Invalid
PLL Unlock
âLâ Output
Invalid
âLâ Output
âLâ Output
PLL Lock
âLâ Output
256fs Output
See Table 9
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
2) PLL Slave Mode (PMPLL bit = â1â, M/S bit = â0â)
In this mode, an invalid clock is output from MCKO pin after PMPLL bit = â0â Ã â1â or sampling frequency is changed.
After that, 256fs is output from MCKO pin when PLL is locked. ADC and DAC output invalid data when the PLL is
unlocked. For DAC, the output signal should be muted by writing â0â to DACA and DACM bits in Addr=02H.
PLL State
After that PMPLL bit â0â Ã â1â
MCKO pin
MCKO bit = â0â MCKO bit = â1â
âLâ Output
Invalid
PLL Unlock
âLâ Output
Invalid
PLL Lock
âLâ Output
256fs Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = â1â, M/S bit = â0â)
MS0396-E-00
- 23 -
2005/06
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