AK4632 Datasheet, PDF (21/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
OPERATION OVERVIEW
„ System Clock
There are the following four clock modes to interface with external devices. (See Table 1 and Table 2)
Mode
PMPLL bit M/S bit PLL3-0 bit
PLL Master Mode
1
1
See Table 4
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1
0
See Table 4
PLL Slave Mode 2
(PLL Reference Clock: FCK or BICK pin)
1
0
See Table 4
EXT Slave Mode
0
0
X
Invalid state (Note 36)
0
1
X
Table 1. Clock Mode Setting (X: Don’t care)
MCKPD bit
0
0
1
0
X
Figure
Figure 19
Figure 20
Figure 21
Figure 22
-
Note 36. If this mode is selected, the invalid clocks are output from MCKO, FCK and BICK pins.
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
MCKO bit MCKO pin MCKI pin
BICK pin FCK pin
0
1
“L” Output
256fs Output
Master Clock
Input for PLL
(Note 37)
16fs/32fs/64fs
Output
1fs
Output
0
1
“L” Output
256fs Output
Master Clock
Input for PLL
(Note 37)
16fs/32fs/64fs
Input
1fs
Input
PLL Slave Mode 2
(PLL Reference Clock: FCK or BICK pin)
0
“L” Output
GND
16fs/32fs/64fs
Input
EXT Slave Mode
256fs/
0
“L” Output
512fs/
1024fs
≥ 32fs
Input
Input
Note 37. 11.2896MHz/12MHz/12.288MHz/13.5MHz/24MHz/27MHz
Table 2. Clock pins state in Clock Mode
1fs
Input
1fs
Input
[Pull-down resistor of MCKI pin]
When the master clock is input, MCKPD bit should be “0”. When the MCKI pin is floating, the pin should be pulled-down
by internal 25kΩ resistor at MCKPD bit = “1”(Default).
MCKI
MCKPD bit ="0"
25kΩ
AK4632
Figure 18. Pull-down resistor of MCKI pin
MS0396-E-00
- 21 -
2005/06