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AK4632 Datasheet, PDF (36/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP
ASAHI KASEI
[AK4632]
„ Speaker Output
The power supply voltage for Speaker-Amp SVDD can be set to from 2.6V to 5.25V. However, SVDD should be set to
from 2.6V to 3.6V, when the load resistance is less than 50Ω(ex. a dynamic speaker).
The output signal from DAC is input to the Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono output
controlled by BTL and a gain of the Speaker-Amp is set by SPKG1-0 bit. In the case of ALC2 OFF, the output voltage
depends on AVDD and SPKG1-0 bits. In the case of ALC2 ON, the output voltage depends on SVDD and SPKG1-0 bits.
The output level of ALC2 is proportional to SVDD.
SPKG1-0 bits
Gain
00
0dB
01
+2.04dB
10
+6.22dB
11
+8.26dB
(Note) These Gain from the level at SPKG1-0bits= “00”.
Table 19. Gain of Speaker-Amp at ALC2 OFF
Output Voltage from Speaker-Amp
Output Voltage from
SPKG1-0 bits AVDD SVDD
at ALC2 OFF and DAC Input=0dBFS Speaker-Amp at ALC ON
00
3.3V
3.3V
3.27Vpp, 167mW@8Ω
3.09Vpp, 150mW@8Ω
01
3.3V
3.3V
4.15Vpp, 269mW@8Ω
3.92Vpp, 240mW@8Ω
10
3.3V
3.3V
6.91Vpp (Note)
Not Available
11
3.3V
3.3V
8.50Vpp (Note)
Not Available
00
3.3V
5.0V
3.27Vpp
Not Available
01
3.3V
5.0V
4.15Vpp
Not Available
10
3.3V
5.0V
6.91Vpp
6.34Vpp
11
3.3V
5.0V
8.50Vpp
8.02Vpp
(Note) This output voltage is assumed that the signal is not clipped. In actual, the signal will be clipped when DAC
outputs 0dBFS signal. The output power is 400mW@8Ω, SVDD=3.3V.
Table 20. Speaker-Amp Output Voltage
[Caution for using Piezo Speaker]
When a piezo speaker (load capacitance > 30pF) is used, resistances more than 10Ω should be inserted between SPP/SPN
pins and speaker in series, respectively, as shown in Figure 35. Zener diodes should be inserted between speaker and
GND as shown in Figure 35, in order to protect SPK-Amp of AK4632 from the power that the piezo speaker outputs
when the speaker is pressured. Zener diodes of the following Zener voltage should be used.
92% of SVDD ≤ Zener voltage of Zener diodo(ZD of Figure 35) ≤ SVDD+0.3V
Ex) In case of SVDD = 5.0V : 4.6V ≤ ZD ≤ 5.3V
For example, Zener diode which Zener voltage is 5.1V(Min :4.97V, Max 5.24V) can be used.
MS0396-E-00
- 36 -
2005/06