AK4632 Datasheet, PDF (25/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
„ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to MCKI, BICK or FCK pin. The required clock to the
AK4632 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency
is 16fs, the audio interface format supports only Mode 0 (DSP Mode).
a) PLL reference clock: BICK or FCK pin
In the case of using BICK as PLL reference clock, the sampling frequency corresponds to 7.35kHz to 48kHz by
changing FS3-0 bits. In the case of using FCK, the sampling frequency corresponds to 7.35kHz to 26kHz. (SeeTable
6)
AK4632
MCKO
MCKI
BICK
FCK
SDTO
SDTI
DSP or µP
16fs, 32fs, 64fs
1fs
BCLK
FCK
SDTI
SDTO
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: FCK or BICK pin)
b) PLL reference clock: MCKI pin
BICK and FCK inputs should be synchronized with MCKO output. The phase between MCKO and FCK dose not
matter. Sampling frequency can be selected by FS3-0 bits. (See Table 5)
AK4632
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or µP
MCKI
MCKO
BICK
FCK
256fs
16fs, 32fs, 64fs
1fs
MCLK
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 21. PLL Slave Mode 2 (PLL Reference Clock: MCKI pin)
The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation
(PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4632 may draw excess current and it is
not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present,
the ADC and DAC should be in the power-down mode (PMADC bit =PMDAC bit = “0”).
MS0396-E-00
- 25 -
2005/06