AK4632 Datasheet, PDF (37/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
SPK-Amp
ZD
≥10Ω
SPP
SPN
≥10Ω
ZD
Figure 35. Circuit of Speaker Output(Load Capacitance > 30pF)
<Control Sequence of Speaker Amp>
Speaker blocks (MOUT, ALC2 and Speaker-amp) can be powered-up/down by controlling the PMSPK bit. When the
PMSPK bit is “0”, the MOUT, SPP and SPN pins are placed in a Hi-Z state.
When the PMSPK bit is “1” and SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is
placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. And then the Speaker output gradually changes to the
SVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4632 is powered-down, pop noise can be
also reduced by first entering power-save-mode.
PMSPK bit
SPPS bit
SPP pin
Hi-Z
Hi-Z
SPN pin Hi-Z ^SVDD/2
SVDD/2
Hi-Z
>t1(Note)
>0
Figure 36. Power-up/Power-down Timing for Speaker-Amp
(Note)
“t1” depends on the time constant of input resistance of MIN and capacitor between MOUT pin and MIN pin. If
Speaker-Amp output is enabled before MIN-Amp (ALC2) becomes stable, pop noise may occur.
Ex) C of MOUT pin – MIN pin = 0.1 µF, Input resistance of MIN pin = 36kΩ(Max) : t1 = 5τ = 18ms
C of MOUT pin – MIN pin and the Input resistance(Rin) of MIN pin compose of HPF which cut off
frequency(fc) are the followings.
fc = 66Hz@Rin=24kΩ(typ), 133Hz@Rin=12kΩ(min), 44Hz@Rin=36kΩ(max)
MS0396-E-00
- 37 -
2005/06