AK4632 Datasheet, PDF (50/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
Addr
06H
Register Name
Timer Select
Default
D7
DVTM
0
D6
ROTM
0
D5
ZTM1
0
D4
ZTM0
0
D3
WTM1
0
D2
WTM0
0
D1
LTM1
0
D0
LTM0
0
LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = “1”) (See Table 35)
The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done
by the period specified by the LTM1-0 bits. Default is “00” (0.5/fs).
LTM1 bit LTM0 bit
ALC1 Limiter Operation Period
8kHz
16kHz
0
0
0.5/fs
63µs
31µs
Default
0
1
1/fs
125µs
63µs
1
0
2/fs
250µs
125µs
1
1
4/fs
500µs
250µs
Table 35. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit=“1”)
WTM1-0: ALC1 Recovery Waiting Period (See Table 36)
A period of recovery operation when any limiter operation does not occur during the ALC1 operation.
Default is “00” (128/fs).
WTM1 bit WTM0 bit ^{ALC1 Recovery Operation Waiting Period}
8kHz
16kHz
0
0
128/fs
16ms
8ms
0
1
256/fs
32ms
16ms
1
0
512/fs
64ms
32ms
1
1
1024/fs
128ms
64ms
Table 36. ALC1 Recovery Operation Waiting Period
Default
ZTM1-0: ALC1 Zero crossing timeout Period (See Table 37)
When the IPGA perform zero crossing or timeout, the IPGA value is changed by the µP WRITE operation,
ALC1 recovery operation or ALC1 limiter operation (ZELM bit = “0”). Default is “00” (128/fs).
ZTM1 bit
0
0
1
1
ZTM0 bit
Zero Crossing Timeout Period
8kHz
16kHz
0
128/fs
16ms
8ms
1
256/fs
32ms
16ms
0
512/fs
64ms
32ms
1
1024/fs
128ms
64ms
Table 37. Zero Crossing Timeout Period
Default
ROTM: Period time for ALC2 Recovery operation, ALC2 Zero Crossing Timeout and ALC2 initializing cycle.
0: 512/fs (Default)
1: 1024/fs
The ROTM bit is set during the PMSPK bit = “0”.
DVTM :Digital Volume Soft Transition Time Control
0: 1061/fs (Default)
1: 256/fs
This is the time to FFH from 00H of DVOL7-0 bits.
MS0396-E-00
- 50 -
2005/06