AK4632 Datasheet, PDF (41/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
„ Video Block
Video-Amp has a drivability for a load resistance of 150Ω. The AK4632 has a composite input and output. A Low Pass
Filter(LPF) and Gain Control Amp(GCA) are integrated and both DC output and Sag Compensation circuit are supported
as shown in Figure 41 and Figure 42. The capacitance for Sag Compensation circuit is 100µ F+2.2µ F or 47µ F+1.0µ F.
When DC output is used, VOUT pin and VSAG pin must be shorted. The output clamp voltage is 150mV(typ) at DC
output. SAGC1-0 bits and VVDD voltage should be set as shown in Table 23. Table 25 shows the gain and step of the
gain control. The gain is set by VGCA4-0 bits. PMV bit controls the power up and down of the video block. VOUT pin
outputs AVSS level at PMV bit = “1”.
YIN
CLAMP
LPF
GCA
C1 _75Ω
-1dB ~ +10.5dB
Step 0.5dB
+6dB ^VOUT
VSAG C2
(C1=100µ F, C2=2.2µ F) or (C1=47µ F, C2=1.0µ F)
Figure 41. Video block (using Sag Compensation circuit)
YIN
CLAMP
LPF
GCA
75Ω
-1dB ~ +10.5dB
Step 0.5dB
+6dB VOUT
VSAG
Figure 42. Video block (at DC Output))
SAGC1 bit
0
0
1
1
SAGC0 bit
VVDD voltage
Output Circuit
0
2.8 V ≤ VVDD ≤ 3.6V
DC output
1
Not Available
0
2.85V ≤ VVDD < 4.75V
Sag compensation
1
4.5 V ≤ VVDD < 5.25V
Sag compensation
Table 23. Setting of VVDD and video output circuit.
Default
Output Circuit
VVDD voltage
GCA setting
DC output
2.8 V ≤ VVDD ≤ 3.6V
0dB
Sag compensation 100µ F+2.2µ F
3.135 V ≤ VVDD ≤ 5.25V
0dB
2.85V ≤ VVDD < 3.135 V
-1dB (Note)
Sag compensation 47µ F+1.0µ F
3.135 V ≤ VVDD ≤ 5.25V
0dB
2.85V ≤ VVDD < 3.135 V
-1dB (Note)
Note : When the sag compensation circuit is used at less than 3.135V of VVDD, the GCA should be set to -1dB in
order to avoid clipping of output video signal. Note that the video will become dark at that time.
Table 24. Gain compensation
MS0396-E-00
- 41 -
2005/06