AK4632 Datasheet, PDF (58/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
2. When the external clocks (FCK or BICK pin) are used in PLL Slave Mode.
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
MCKPD bit
(Addr:01H, D2)
PMPLL bit
(Addr:01H, D0)
FCK pin
BICK pin
Internal Clock
(1)
(2) (3)
Example:
Audio I/F Format : DSP Mode, BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
4f₍s₁o₎ f_{Power Supply & PDN pin = “L” Æ “H”}
(4) "H"
(2) Addr:04H, Data:30H
Addr:05H, Data:00H
(3) Addr:00H, Data:40H
Input
(5)
(4) Addr:01H, Data:05H
(6)
BICK and FCK input
Figure 47. Clock Set Up Sequence (2)
<Example>
(1)After Power Up: PDN pin “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4632.
(2) DIF1-0, FS3-0, PLL3-0, MSBS and BCKP bits should be set during this period.
(3)Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4)Pull down of the MCKI pin: MCKPD bit = “1”
(5)PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (FCK or BICK pin) is supplied.
PLL lock time is 160ms(max) when FCK is a PLL reference clock. And PLL lock time is 2ms(max) when BICK
is a PLL reference clock.
(6)Normal operation stats after the PLL is locked.
MS0396-E-00
- 58 -
2005/06