AK4632 Datasheet, PDF (59/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
3. When the external clock (MCKI pin) is used in PLL Slave Mode.
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
MCKPD bit
(Addr:01H, D2)
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
MCKI pin
MCKO pin
BICK pin
FCK pin
(1)
(2) (3)
(4)
(5)
(6)
Input
40msec(max)
(7)
(8)
(9)
Output
Input
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO : Enable
Sampling Frequency:8kHz
(1) Power Supply & PDN pin = “L” Æ “H”
(2)Addr:01H, Data:04H
Addr:04H, Data:48H
Addr:05H, Data:00H
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:03H
MCKO output start
BICK and FCK input start
Figure 48. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4632.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4) Release the pull-down resistor of the MCKI pin: MCKPD bit = “1” → “0”
(5) Enable MCKO output: MCKO bit = “1”
(6) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied. PLL
lock time is 40ms(max).
(7) The normal clock is output from MCKO after PLL is locked.
(8) The invalid frequency is output from MCKO during this period.
(9) BICK and FCK clocks should be synchronized with MCKO clock.
MS0396-E-00
- 59 -
2005/06