AK4632 Datasheet, PDF (44/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
„ Register Definitions
Addr
00H
Register Name
Power Management 1
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
PMVCM PMBP PMSPK PMAO PMDAC PMMIC PMADC
0
0
0
0
0
0
0
0
PMADC: ADC Block Power Control
0: Power down (Default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle (1059/fs=133ms@8kHz) starts. After
initializing, digital data of the ADC is output.
PMMIC: MIC In Block (MIC-Amp and ALC1) Power Control
0: Power down (Default)
1: Power up
PMDAC: DAC Block Power Control
0: Power down (Default)
1: Power up
PMAO: Mono Line Out Power Control
0: Power down (Default)
1: Power up
PMSPK: Speaker Block Power Control
0: Power down (Default)
1: Power up
PMBP: BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBP bit is “0”, the path is still connected between BEEP and AOUT/SPK-Amp. BEEPS and BEEPA
bits should be set to “0” to disconnect these paths.
PMVCM: VCOM Block Power Control
0: Power down (Default)
1: Power up
Each block can be powered-down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are
powered-down.
When PMPLL and MCKO bits and all bits in 00H address are “0”, all blocks are powered-down. Though the IPGA
resisters are initialized, the other registers remain unchanged. (refer to the IPGA6-0 bits description)
When any of the blocks are powered-up, the PMVCM bit must be set to “1”. When PMPLL and MCKO bits and all
bits in 00H address are “0”, PMVCM bit can write to “0”.
When BEEP signal is output from Speaker-Amp (Signal path: BEEP pin Æ SPP/SPN pins) or Mono Lineout-Amp
(Signal path: BEEP pin Æ AOUT pin) only, the clocks may not be present. When ADC, DAC, ALC1 or ALC2 is in
operation, the clocks must always be present.
MS0396-E-00
- 44 -
2005/06