AK4632 Datasheet, PDF (67/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
„ Stop of Clock
Master clock can be stopped when ADC, DAC, ALC1, ALC2 and IPGA don’t operate.
1. In case of PLL Master Mode
PMPLL bit
(Addr:01H,D0)
MCKO bit
(Addr:01H,D1)
MCKPD bit
(Addr:01H,D2)
External MCKI
(1)
(2)
"H" or "L"
(3)
(4)
Input
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Sampling Frequency:8kHz
(1) (2) (3) Addr:01H, Data:0CH
Stop an external MCKI
Figure 56. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Pull down the MCKI pin: MCKPD bit = “0” → “1”
When the external master clock becomes Hi-Z, MCKI pin should be pulled down.
(4) Stop an external master clock.
2. When an external clocks (FCK or BICK pins) are used in PLL Slave Mode.
PMPLL bit
(Addr:01H,D0)
External BICK
External FCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format : DSP Mode, BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1) Addr:01H, Data:04H
(2) Stop the external clocks
Figure 57. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and FCK clocks
MS0396-E-00
- 67 -
2005/06