AK4632 Datasheet, PDF (57/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
CONTROL SEQUENCE
„ Clock Set up
When ADC, DAC, ALC1, ALC2 and IPGA are used, the clocks must be supplied.
1. In case of PLL Master Mode.
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
MCKPD bit
(Addr:01H, D2)
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
MCKI pin
M/S bit
(Addr:01H, D3)
BICK pin
FCK pin
MCKO pin
(1)
(2) (3)
(4)
(5)
(6)
Input
40msec(max)
(7)
(8)
Output
1msec (max)
40msec(max)
(9)
(10)
Output
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO : Enable
Sampling Frequency:8kHz
(1) Power Supply & PDN pin = “L” Æ “H”
(2)Addr:01H, Data:0CH
Addr:04H, Data:48H
Addr:05H, Data:00H
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:0BH
MCKO, BICK and FCK output
Figure 46. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4632.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.
(3) Power UpVCOM: PMVCM bit = “0” → “1”
VCOM should first be powered-up before the other block operates.
(4) Release the pull-down resistor of the MCKI pin: MCKPD bit = “1” → “0”
(5) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(6) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(7) The AK4632 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of
the block which a clock is necessary for becomes possible.
(8) The invalid frequencies are output from FCK and BICK pins during this period.
(9) The invalid frequency is output from MCKO pin during this period.
(10) The normal clock is output from MCKO pin after the PLL is locked.
MS0396-E-00
- 57 -
2005/06