AK4632 Datasheet, PDF (27/70 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK/Video-AMP

ASAHI KASEI
[AK4632]
„ Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits. (See Table 12) In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and
BICK are output from AK4632 in master mode, but must be input to AK4632 in slave mode.
In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC) SDTI (DAC)
BICK
DSP Mode
DSP Mode
≥ 16fs
MSB justified MSB justified ≥ 32fs
MSB justified MSB justified
I²S compatible I²S compatible
≥ 32fs
≥ 32fs
Table 12. Audio Interface Format
Figure
See Table 13
Figure 27
Figure 28
Figure 29
Default
In Mode0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge of BICK, SDTI data is latched by falling edge of BICK.
When BCKP bit is “1”, SDTO data is output by falling edge of BICK, SDTI data is latched by rising edge of BICK.
MSB data position of SDTO and SDTI can be shifted by MSBS bit. The shifted period is a half of BICK.
MSBS bit BCKP bit
Audio Interface Format
0
0
Figure 23
0
1
Figure 24
1
0
Figure 25
1
1
Figure 26
Table 13. Audio Interface Format in Mode 0
Default
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1” at
8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data and
this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
„ System Reset
Upon power-up, reset the AK4632 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their
initial values.
The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle
time is 1059/fs, or 133ms@fs=8kHz. During the initialization cycle, the ADC digital data outputs of both channels are
forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete.
The DAC does not require an initialization cycle.
MS0396-E-00
- 27 -
2005/06