Z8S18020FSC Datasheet, PDF (64/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
OPERATION MODE CONTROL REGISTER
Mnemonic OMCR
Address 3E
The Z80180/Z8S180/Z8L180 is descended from two dif-
ferent “ancestor” processors, Zilog's original Z80 and the
Hitachi 64180. The Operating Mode Control Register (OM-
CR) can be programmed to select between certain differ-
ences between the Z80 and the 64180.
D7 D6 D5 -- -- -- -- --
Reserved
IOC (R/W)
M1TE (W)
M1E (R/W)
Zilog
M1E (M1 Enable). This bit controls the M1 output and is
set to a 1 during reset.
When M1E=1, the M1 output is asserted Low during the
opcode fetch cycle, the INT0 acknowledge cycle, and the
first machine cycle of the NMI acknowledge.
On the Z80180/Z8S180/Z8L180, this choice makes the
processor fetch an RETI instruction once, and when fetch-
ing an RETI from zero-wait-state memory will use three
clock machine cycles which are not fully Z80-timing com-
patible but are compatible with the on-chip CTCs.
When MIE=0, the processor does not drive M1 Low during
instruction fetch cycles, and after fetching an RETI instruc-
tion once with normal timing, it goes back and re-fetches
the instruction using fully Z80-compatible cycles that in-
clude driving M1 Low. This may be needed by some exter-
nal Z80 peripherals to properly decode the RETI instruc-
tion.I/O Control Register (ICR).
Figure 82. Operating Control Register
(OMCR: I/O Address = 3EH)
φ
A₀-A₁₈ (A₁₉)
D₀-D₇
M1
T₁ T₂ T₃ T₁ T₂ T₃ T_I T_I
PC
EDH
PC+1
4DH
T_I T₁ T₂ T₃ T_I T₁ T₂ T₃ T_I
PC
EDH
PC+1
4DH
MREQ
RD
ST
Figure 83. RETI Instruction Sequence with MIE=0
ICR allows relocating of the internal I/O addresses. ICR also controls enabling/disabling of the IOSTOP mode (Figure 84).
1-64
Bit 7
6
5
4
3
2
1
0
IOA7 IOA6 IOSTP --
--
--
--
--
R/W R/W R/W
Figure 84. I/O Control Register (ICR: I/O Address = 3FH)
PRELIMINARY
DS971800401