English
Language : 

Z8S18020FSC Datasheet, PDF (27/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR
Zilog
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
AC CHARACTERISTICS
(VCC = 5V ±10% or VCC = 3.3V ±10% over specified temperature range, unless otherwise noted, 33
MHZ characteristics apply only to 5V operation.)
1
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
26a.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
Symbol
tcyc
tCHW
tCLW
tcf
tcr
tAD
tAS
tMED1
tRDD1
tM1D1
tAH
tMED2
tRDD2
tM1D2
tDRS
tDRH
tSTD1
tSTD2
tWS
tWH
tWDZ
tWRD1
tWDD
tWDS
tWRD2
tWRP
tWDH
tIOD1
tIOD2
tIOD3
tINTS
tINTS
tNMIW
tBRS
tBRH
tBAD1
tBAD2
Item
Clock Cycle Time
Clock “H” Pulse Width
Clock “L” Pulse Width
Clock Fall Time
Clock Rise Time
ØRise to Address Valid Delay
Address Valid to /MREQ Fall or /IORQ Fall)
Ø Fall to /MREQ Fall Delay
Ø Fall to /RD Fall Delay /IOC = 1
Ø Rise to /RD Rise Delay /IOC = 0
Ø Rise to /M1 Fall Delay
Address Hold Time from
(/MREQ, /IOREQ, /RD, /WR)
Ø Fall to /MREQ Rise Delay
Ø Fall to /RD Rise Delay
Ø Rise to /M1 Rise Delay
Data Read Set-up Time
Data Read Hold Time
Ø Fall to ST Fall Delay
Ø Fall to ST Rise Delay
/WAIT Set-up Time to Ø Fall
/WAIT Hold Time from Ø Fall
Ø Rise to Data Float Delay
Ø Rise to /WR Fall Delay
Ø Fall to Write Data Delay Time
Write Data Set-up Time to /WR Fall
Ø Fall to /WR Rise Delay
/WR Pulse Width
/WR Pulse Width (I/O Write Cycle)
Write Data Hold Time from (/WR Rise)
Ø Fall to /IORQ Fall Delay /IOC = 1
Ø Rise to /IORQ Fall Delay /IOC = 1
Ø Fall to /IORQ Rise Delay
/M1 Fall to /IORQ Fall Delay
/INT Set-up Time to Ø Fall
/INT Hold Time from Ø Fall
/NMI Pulse Width
/BUSREQ Set-up Time to Ø Fall
/BUSREQ Hold Time from Ø Fall
Ø Rise to /BUSACK Fall Delay
Ø Fall to /BUSACK Rise Delay
Z80180-20
Min.
Max.
50
2000
15
–
15
–
–
10
–
10
–
15
20
–
–
15
–
15
–
15
–
15
–
20
–
15
–
15
–
15
15
–
0
–
–
15
–
15
15
–
5
–
–
10
–
15
–
20
10
–
–
15
70
–
120
–
5
–
–
15
–
15
–
15
120
–
15
–
10
–
35
–
10
–
10
–
–
15
–
15
Z80180-33
Min.
Max.
Unit
33
2000
ns
10
–
ns
10
–
ns
–
5
ns
–
5
ns
–
15
ns
5
–
ns
–
15
ns
–
15
ns
–
15
–
15
ns
5
–
ns
–
15
ns
–
15
ns
–
15*
ns
15
–
ns
0
–
ns
–
15
ns
–
15
ns
15
–
ns
5
–
ns
–
10
ns
–
15
ns
–
20
ns
0
–
ns
–
15
ns
40
–
ns
70
–
ns
5
–
–
15
ns
–
15
–
15
ns
70
–
ns
15
–
ns
10
–
ns
25
–
ns
10
–
ns
10
ns
–
15
ns
–
15
ns
DS971800401
PRELIMINARY
1-27