Z8S18020FSC Datasheet, PDF (42/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
PE: Parity Error (bit 5). A parity error is detected when
parity checking is enabled by the MOD1 bit in the CNT1LA
register being 1, and a character has been assembled in
which the parity does not match the PEO bit in the CNTLB
register. However, this status bit is not set until/unless the
error character becomes the oldest one in the RxFIFO. PE
is cleared when software writes a 1 to the EFR bit in the
CNTRLA register, and also by Reset, in IOSTOP mode,
and for ASCI0 if the /DCD0 pin is auto-enabled and is ne-
gated (High).
FE: Framing Error (bit 4). A framing error is detected
when the stop bit of a character is sampled as 0/Space.
However, this status bit is not set until/unless the error
character becomes the oldest one in the RxFIFO. FE is
cleared when software writes a 1 to the EFR bit in the
CNTLA register, and also by Reset, in IOSTOP mode, and
for ASCIO if the /DCDO pin is auto-enabled and is negated
(High).
REI: Receive Interrupt Enable (bit 3). RIE should be set
to 1 to enable ASCI receive interrupt requests. When RIE
is 1, the Receiver requests an interrupt when a character
is received and RDRF is set, but only if neither DMA chan-
nel has its Request-routing field set to receive data from
this ASCI. That is, if SM1-0 are 11 and SAR17-16 are 10,
or DIM1 is 1 and IAR17-16 are 10, then ASCI1 doesn't re-
quest an interrupt for RDRF. If RIE is 1, either ASCI re-
quests an interrupt when OVRN, PE or FE is set, and
ASCI0 requests an interrupt when /DCD0 goes High. RIE
is cleared to 0 by Reset.
DCD0: Data Carrier Detect (bit 2 STAT0). This bit is set
to 1 when the pin is High. It is cleared to 0 on the first read
of STAT0 following the pin's transition from High to Low
and during RESET. Bit 6 of the ASEXT0 register is 0 to se-
lect auto-enabling, and the pin is negated (High). Channel
1 has an external CTS1 input which is multiplexed with the
receive data pin RSX for the CSI/O.
Bit 2 = 0; Select RXS function.
Bit 2 = 1; Select CTS1 function.
TDRE: Transmit Data Register Empty (bit 1). TDRE = 1
indicates that the TDR is empty and the next transmit data
byte is written to TDR. After the byte is written to TDR,
TDRE is cleared to 0 until the ASCI transfers the byte from
TDR to the TSR and then TDRE is again set to 1. TDRE is
set to 1 in IOSTOP mode and during RESET. On ASCIO,
if the CTS0 pin is auto-enabled in the ASEXT0 registers
and the pin is High, TDRE is reset to 0.
TIE: Transmit Interrupt Enable (bit 0). TIE should be set
to 1 to enable ASCI transmit interrupt requests. If TIE = 1,
an interrupt will be requested when TDRE = 1. TIE is
cleared to 0 during RESET.
ASCI TRANSMIT DATA REGISTERS
Register addresses 06H and 07H hold the ASCI transmit
data for channel 0 and channel 1, respectively.
Channel 0
Mnemonics TDR0
Address (06H)
76
-- --
54
-- --
32
-- --
10
-- --
ASCI Transmit
Channel 0
Channel 1
Mnemonics TDR1
Address (07H)
76
-- --
54
-- --
32
-- --
10
-- --
ASCI Transmit
Channel 1
Figure 37. ASCI Register
Figure 36. ASCI Register
1-42
PRELIMINARY
DS971800401