Z8S18020FSC Datasheet, PDF (40/70 Pages) Zilog, Inc. – ENHANCED Z180 MICROPROCESSOR

Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
MOD2, 1, 0: ASCI Data Format Mode 2, 1, 0 (bits 2-0).
These bits program the ASCI data format as follows.
MOD2
= 0→7 bit data
= 1→8 bit data
MOD1
= 0→No parity
= 1→Parity enabled
MOD0
= 0→1 stop bit
= 1→2 stop bits
The data formats available based on all combinations of
MOD2, MOD1, and MOD0 are shown in Table 5-6.
Table 5. Data Formats
MOD2 MOD1 MOD0 Data Format
0
0
0 Start + 7 bit data + 1 stop
0
0
1 Start + 7 bit data + 2 stop
0
1
0 Start + 7 bit data + parity + 1 stop
0
1
1 Start + 7 bit data + parity + 2 stop
1
0
0 Start + 8 bit data + 1 stop
1
0
1 Start + 8 bit data + 2 stop
1
1
0 Start + 8 bit data + parity + 1 stop
1
1
1 Start + 8 bit data + parity + 2 stop
ASCI CHANNEL CONTROL REGISTER B
ASCI Control Register B 0 (CNTLB0: I/O Address = 02H)
ASCI Control Register B 1 (CNTLB1: I/O Address = 03H)
Bit
7
6
5
4
3
2
1
0
CTS/
MPBT MP
PS
PEO
DR
SS2
SS1 SS0
R/W
R/W R/W R/W R/W
R/W R/W
R/W
Figure 34. ASCI Channel Control Register B
MPBT: Multiprocessor Bit Transmit (bit 7). When multi-
processor communication format is selected (MP bit = 1),
MPBT is used to specify the MPB data bit for transmission.
If MPBT = 1, then MPB = 1 is transmitted. If MPBT = 0,
then MPB = 0 is transmitted. MPBT state is undefined dur-
ing and after RESET.
MP: Multiprocessor Mode (bit 6). When MP is set to 1,
the data format is configured for multiprocessor mode
based on the MOD2 (number of data bits) and MOD0
(number of stop bits) bits in CNTLA. The format is as fol-
lows.
Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits
Note that multiprocessor (MP=1) format has no provision
for parity. If MP = 0, the data format is based on MOD0,
MOD1, MOD2, and may include parity. The MP bit is
cleared to 0 during RESET.
CTS/PS: Clear to Send/Prescale (bit 5). When read,
/CTS/PS reflects the state of the external /CTS input. If the
/CTS input pin is HIGH, /CTS/PS will be read as 1. Note
that when the /CTS input pin is HIGH, the TDRE bit is in-
hibited (i.e. held at 0). For channel 1, the /CTS input is mul-
tiplexed with RXS pin (Clocked Serial Receive Data).
Thus, /CTS/PS is only valid when read if the channel 1
CTS1E bit = 1 and the /CTS input pin function is selected.
The read data of /CTS/PS is not affected by RESET.
If the SS2-0 bits in this register are not 111, and the BRG
mode bit in the ASEXT register is 0, then writing to this bit
sets the prescale (PS) control as described in the following
“Clock Modes” section. Under those circumstances, a 0 in-
dicates a divide by 10 prescale function while a 1 indicates
divide by 30. The bit resets to 0.
PEO: Parity Even Odd (bit 4). PEO selects oven or odd
parity. PEO does not affect the enabling/disabling of parity
(MOD1 bit of CNTLA). If PEO is cleared to 0, even parity
is selected. If PEO is set to 1, odd parity is selected. PEO
is cleared to 0 during RESET.
DR: Divide Ratio (bit 3). If the X1 bit in the ASEXT regis-
ter is 0, this bit specifies the divider used to obtain baud
rate from the data sampling clock. If DR is reset to 0, di-
vide- by-16 is used, while if DR is set to 1 divide-by-64 is
used. DR is cleared to 0 during RESET.
SS2,1,0: Source/Speed Select 2,1,0 (bits 2-0). First, if
these bits are 111, as they are after a Reset, the CKA pin
1-40
PRELIMINARY
DS971800401